Method for manufacturing a pixel sensing circuit
View Patent ↗Systems and methods of pixel sensing circuits. In accordance with a first embodiment of the present invention, a pixel sensing circuit includes a floating diffusion functionally coupled to and surrounded by a ring transfer transistor. The ring transfer transistor is functionally coupled to and surrounded by a photo diode. The photo diode may be surrounded by a region of poly silicon. The disclosed structure provides radiation hardening and low light performance.
1. A method for manufacturing a pixel sensing circuit, comprising:
providing a semiconductor material of a first conductivity type;
forming a gate structure configured as an enclosed geometric structure over a portion of the semiconductor material, the gate structure having an interior side and an exterior side;
forming a first doped region of a second conductivity type adjacent the interior side of the gate structure;
forming a second doped region of the second conductivity type adjacent the exterior side of the gate structure, wherein the gate structure and the first and second doped regions form a transfer transistor and wherein the first doped region serves as a charge storage element; and
forming a third doped region of the first conductivity type adjacent the exterior side of the gate structure and laterally surrounding the gate structure, wherein the third doped region, the second doped region, and a portion of the semiconductor material form a photo diode region, and wherein a reset transistor is formed outside the photo diode region.
2. The method of claim 1 , wherein the first conductivity type is p-type conductivity and the second conductivity type is n-type conductivity.
3. The method of claim 1 , further including forming a poly silicon structure surrounding the third doped region.
4. The method of claim 1 , further including forming a fourth doped region of the first conductivity type in the semiconductor material.
5. The method of claim 4 , wherein forming the third doped region includes forming a first portion of the third doped region in a portion of the fourth doped region and forming a second portion of the third doped region in a portion of the second doped region.
6. The method of claim 1 , wherein forming the gate structure includes forming the gate structure to have a ring configuration.
7. The method of claim 1 , further including configuring the gate structure and the first and second doped regions as a MOSFET transistor having an enclosed geometry.
8. The method of claim 1 , further including coupling an amplifier to the charge storage element.
9. The method of claim 8 , wherein the amplifier is a transistor configured as a source follower.
10. The method of claim 1 , further including coupling the reset transistor to the charge storage element.
11. The method of claim 1 , further including coupling an amplifier to the reset transistor, wherein the amplifier is outside the photodiode region.