MRAM with sidewall protection and method of fabrication
View Patent ↗BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.
1. A memory cell comprising:
a memory device stack including a top electrode, a memory element having a plurality of layers, and a bottom electrode;
a sidewall protection sleeve of a first dielectric material encircling sidewalls of the memory element, the bottom electrode, and a lower portion of the top electrode, the sidewall protection sleeve generally conforming to a shape of the memory element in a plane parallel to a surface of a substrate and having a generally conical shape with an open top through which an upper surface of the top electrode protrudes; and
a metal bit line interconnect in electrical contact with the upper surface of the top electrode, the metal bit line interconnect being formed in a via that is wider than the upper surface of top electrode and extends below an upper edge of the sidewall protection sleeve, the metal bit line interconnect covering the upper surface of the top electrode and extending down below a plane of the upper surface of the top electrode to make contact with and surround an upper portion of the sidewall protection sleeve.
2. The memory cell of claim 1 further comprising an etch-stop layer that forms at least a portion of sidewalls of the via for the metal bit line interconnect and the etch stop layer making contact with a lower portion of the sidewall protection sleeve below the via, the etch-stop layer consisting of a selected dialectic material, and wherein the first dielectric material in the sidewall protection sleeve has a lower etching rate than the selected dielectric material in the etch-stop layer in a selected etching gas used to etch the etch-stop layer to create the via for the metal bit line interconnect.
3. The memory cell of claim 1 wherein the sidewall protection sleeve includes a layer of aluminum oxide.
4. The memory cell of claim 1 wherein the sidewall protection sleeve includes a layer of a borazinic film.
5. The memory cell of claim 1 wherein the sidewall protection sleeve substantially covers a sidewall of the top electrode.
6. The memory cell of claim 1 wherein the sidewall protection sleeve includes an outer layer of the first dielectric material and an inner layer of a second dielectric material and wherein the inner layer is in contact with the sidewalls of the memory element and the bottom electrode.
7. The memory cell of claim 6 wherein the inner layer is an oxygen-free dielectric.
8. The memory cell of claim 7 wherein the outer layer is aluminum oxide.
9. The memory cell of claim 7 wherein the outer layer is a borazinic film.