IP Library Granted Patent US 8,859,396
Granted Patent B2
US 8,859,396 · App. 13/156,636 · Granted Oct 14, 2014

Semiconductor die singulation method

Inventors: Gordon M. Grivna (Mesa, AZ); John M. Parsey, Jr. (Phoenix, AZ)
Assignee: Semiconductor Components Industries, LLC
H01L21/78H04L21/67063
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Quick Facts
Patent No.
US 8,859,396
App. No.
13/156,636
Granted
Oct 14, 2014
Kind
B2
Abstract

In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.

Claims (25)

1. A method of singulating semiconductor die from a semiconductor wafer, the method comprising:

providing the semiconductor wafer formed from a silicon semiconductor material and having a plurality of semiconductor dies formed on a first surface of the semiconductor wafer, the plurality of semiconductor dies separated from each other by singulation regions where singulation openings are to be formed wherein the plurality of semiconductor dies include a dielectric layer overlying portions of the plurality of semiconductor dies, the semiconductor wafer including a second surface that is opposite to the first surface;

forming a conductor on the second surface of the semiconductor wafer, the conductor having a thickness;

reducing the thickness of portions of the conductor to form a reduced thickness region of the conductor;

attaching the semiconductor wafer to a carrier tape wherein the conductor overlies the carrier tape; and

etching a first opening to extend into the semiconductor wafer thereby creating a space between the plurality of semiconductor dies wherein the carrier tape remains attached during the etching.

2. The method of claim 1 further including separating one semiconductor die of the plurality of semiconductor dies from the carrier tape and from other die of the plurality of semiconductor dies wherein a first portion of the conductor remains attached to the one semiconductor die and is separated from other portions of the conductor along the reduced thickness region.

3. The method of claim 2 wherein separating one semiconductor die includes using a pick-and-place operation to detach the semiconductor die from the carrier tape and to detach the first portion of the conductor underlying the semiconductor die from other portions of the conductor.

4. The method of claim 1 wherein etching the first opening includes etching the first opening from the first surface of the semiconductor wafer through the semiconductor wafer to the second surface.

5. The method of claim 1 wherein reducing the thickness of the portions of the conductor to form the reduced thickness regions includes forming the reduced thickness regions in the portions of the conductor that underlie the singulation regions.

6. The method of claim 1 wherein reducing the thickness forms openings through the conductor and exposes portions of the second surface of the semiconductor wafer.

7. The method of claim 1 wherein forming the conductor forms a portion of the second surface into a metal-silicon alloy and wherein reducing the thickness forms the reduced thickness regions to extend through the conductor down to the metal-silicon alloy.

8. The method of claim 1 wherein creating the space between the plurality of semiconductor dies includes forming the space with a width that is greater than a width of the reduced thickness regions.

9. The method of claim 1 wherein etching the first opening includes using the carrier tape for supporting the plurality of semiconductor dies after forming the space between the plurality of semiconductor dies.

10. The method of claim 1 wherein etching the first opening includes etching the first opening to expose a surface of the semiconductor wafer; and

etching through the first opening to extend a depth of the first opening into the semiconductor wafer thereby creating the space between the plurality of semiconductor dies wherein the carrier tape remains attached during the etching.

11. A method of singulating semiconductor die from a semiconductor wafer, the method comprising:

providing the semiconductor wafer formed from a silicon semiconductor material and having a plurality of semiconductor dies formed on a first surface of the semiconductor wafer and separated from each other by singulation regions of the semiconductor wafer where singulation openings are to be formed, the semiconductor wafer including a second surface that is opposite to the first surface;

providing a material on the second surface of the semiconductor wafer, the material having a thickness;

engaging a cutting tool with the material to reduce the thickness of portions of the material, the cutting tool having a cutting tip and cutting surfaces that penetrate into the material to form reduced thickness regions in the material; and

moving the cutting tool across the material to form the reduced thickness regions.

12. The method of claim 11 wherein engaging the cutting tool with the material includes engaging the cutting tool having an accumulation region which has a recess with a volume for accepting portions of the material forced up from the surface of the material by the penetration.

13. The method of claim 11 wherein engaging the cutting tool with the material includes engaging the cutting tool having a depth stop to limit a distance of penetration into the conductor.

14. The method of claim 11 wherein providing the material on the second surface includes providing a conductor on the second surface.

15. The method of claim 11 wherein engaging a cutting tool with the material includes reducing the thickness of multiple portions of the material simultaneously.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2011
From: GRIVNA, GORDON M.; PARSEY, JOHN M., JR.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026416/0887 →
Continuity (3)
Continuation In Part 12749370 · Mar 29, 2010
Continuation 11834924 · Aug 7, 2007
Related Publication 20110244657A1 · Oct 6, 2011