Identification of dies on a semiconductor wafer
View Patent ↗A semiconductor wafer includes multiple dies and a die identification region adjacent to or on each die. The die identification region can include a wafer indicator and a pattern of die locations representing die locations on the wafer. A die identification marker is provided in each pattern of die locations in the die identification region specifying a location of a respective die on the wafer.
1. A method for identifying a location, relative to a particular wafer edge, in which a die on a semiconductor wafer is fabricated, the wafer including a plurality of dies having locations that form a wafer pattern, the method comprising:
providing a pattern layer on the semiconductor wafer;
patterning the pattern layer to provide a die identification region adjacent to or on the die on the semiconductor wafer, wherein the die identification region includes a wafer indicator and a duplicate wafer pattern, the wafer indicator indicating an orientation of the duplicate wafer pattern relative to the particular wafer edge;
providing a marker layer over the die identification region;
providing a die identification marker in the marker layer over a respective die location in the duplicate wafer pattern identifying a location of the die on the semiconductor wafer;
separating the die from the semiconductor wafer and the other dies; and
thereafter, examining the die identification region on the die to identify the location, relative to the particular wafer edge, in which the die was fabricated based only on the wafer indicator and the respective die location indicated by the die identification marker.
2. The method as in claim 1 , wherein patterning the pattern layer to provide a die identification region adjacent to or on the die on the semiconductor wafer comprises:
depositing a pattern layer;
providing a masking layer over the pattern layer;
patterning the masking layer;
removing portions of the pattern layer to provide the die identification region adjacent to or on the die on the semiconductor wafer; and
removing the masking layer.
3. The method as in claim 1 , wherein patterning the marker layer to provide a die identification marker in the marker layer over a respective die location in the duplicate wafer pattern identifying a location of the die on the semiconductor wafer comprises:
depositing a marker layer
providing a masking layer over the marker layer;
patterning the masking layer;
removing portions of the marker layer to provide the die identification region adjacent to or on the die on the semiconductor wafer; and
removing the masking layer.
4. The method as in claim 1 , wherein the pattern layer comprises a metal layer.
5. The method as in claim 1 , wherein the marker layer comprises a passivation layer.
6. The method as in claim 1 , wherein the duplicate wafer pattern contains only die locations corresponding to locations on the semiconductor wafer in which dies are fabricated.