Bridge circuits and their components
A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor.
1. A half bridge comprising:
a first switch comprising a first transistor and a second switch comprising a second transistor, wherein
a source of the first switch is connected to a drain of the second switch,
the first or second transistor comprises a channel and lacks an intrinsic diode anti-parallel to the channel,
the first switch further comprises a third transistor having a terminal connected to the first transistor, and
the third transistor includes a parasitic diode and the half bridge includes a low voltage diode connected in parallel to the parasitic diode.
2. The half bridge of claim 1 , wherein the terminal of the third transistor is a source, a gate of the first transistor is electrically connected to the source of the third transistor, and a source of the first transistor is electrically connected to a drain of the third transistor.
3. The half bridge of claim 1 , wherein the first transistor is a high voltage transistor and the third transistor is a low voltage transistor.
4. The half bridge of claim 1 , wherein the first transistor is a depletion mode transistor and the third transistor is an enhancement mode transistor.
5. The half bridge of claim 4 , wherein the first transistor is a III-N transistor.
6. The half bridge of claim 4 , wherein the third transistor is a III-N transistor.
7. The half bridge of claim 4 , wherein the third transistor is a nitrogen face III-N HEMT.
8. The half bridge of claim 4 , wherein the third transistor is a silicon based transistor.
9. The half bridge of claim 8 , wherein the third transistor is a silicon MOSFET.
10. The half bridge of claim 1 , wherein the first or second transistor is a III-N transistor.
11. The half bridge of claim 1 , wherein the first or second transistor is a HEMT.
12. The half bridge of claim 1 , wherein the first or second transistor is capable of conducting current through the channel in a first direction and in a second direction.
13. The half bridge of claim 1 , wherein the first or second transistor is a depletion mode device.
14. The half bridge of claim 1 , wherein the first or second transistor is an enhancement mode device.
15. A half bridge comprising a first transistor and a second transistor, the first transistor having a gate, a source, a drain, a channel, and a threshold voltage, wherein the first transistor is configured to conduct substantial current through the channel in a first direction both when the gate is biased relative to the source at a voltage higher than the threshold voltage and when the gate is biased relative to the source at a voltage lower than the threshold voltage.
16. The half bridge of claim 15 , wherein the first transistor is further configured to block a substantial voltage between the source and the drain in a second direction when the gate is biased relative to the source at a voltage lower than the threshold voltage.
17. The half bridge of claim 15 , wherein the first transistor is further configured to conduct substantial current in a second direction when the gate is biased relative to the source at a voltage higher than the threshold voltage.
18. The half bridge of claim 15 , wherein the first transistor is a III-N transistor.
19. The half bridge of claim 15 , wherein the first transistor is a HEMT.
20. The half bridge of claim 15 , wherein the half bridge is free of diodes.
21. The half bridge of claim 15 , the second transistor having a terminal, wherein the terminal of the second transistor is connected to the first transistor.
22. The half bridge of claim 21 , wherein the terminal of the second transistor is a source, the gate of the first transistor is electrically connected to the source of the second transistor, and the source of the first transistor is electrically connected to a drain of the second transistor.
23. The half bridge of claim 21 , wherein the first transistor is a high voltage transistor and the second transistor is a low voltage transistor.
24. The half bridge of claim 21 , wherein the first transistor is a depletion mode transistor and the second transistor is an enhancement mode transistor.
25. The half bridge of claim 24 , wherein the first transistor is a III-N transistor.
26. The half bridge of claim 24 , wherein the second transistor is a III-N transistor.
27. The half bridge of claim 24 , wherein the second transistor is a nitrogen face III-N HEMT.
28. The half bridge of claim 24 , wherein the second transistor is a silicon based transistor.
29. The half bridge of claim 28 , wherein the second transistor is a silicon MOSFET.
30. The half bridge of claim 21 , wherein the second transistor includes a parasitic diode and the half bridge includes a low voltage diode connected in parallel to the parasitic diode.