A process for fabricating a semiconductor device. The process including (a) growing a channel layer on a buffer layer, (b) growing a barrier layer on the channel layer, (c) epitaxially growing a quaternary etch-stop layer on the barrier layer, (d) growing a first contact layer on the quaternary etch-stop layer, (e) growing a second contact layer on the first contact layer, (f) etching portions of the second contact layer to reveal a first recess surface, and (g) etching portions of the first contact layer to reveal a second recess surface. The second contact layer may be a highly doped contact layer. The second recess surface generally forms a gate region. The first and the second contact layers have a first etch rate and the quaternary etch-stop layer has a second etch rate in a chosen first etch chemistry.
1. A process for fabricating a semiconductor device, the process comprising:
growing an n-channel layer on a buffer layer;
growing a barrier layer on said n-channel layer;
epitaxially growing a quaternary etch-stop layer on said barrier layer;
growing a first contact layer on said quaternary etch-stop layer;
growing a second contact layer on said first contact layer, said second contact layer being a highly doped contact layer;
etching portions of said second contact layer to reveal a first recess surface; and
etching portions of said first contact layer to reveal a second recess surface, said second recess surface forming a gate region, wherein said first and said second contact layers have a first etch rate and said quaternary etch-stop layer has a second etch rate in a chosen first etch chemistry.
2. The process according to claim 1 , wherein etching portions of said second contact layer to reveal said first recess surface and etching portions of said first contact layer to reveal said second recess surface further comprise a photolithographic process.
3. The process according to claim 1 , wherein said quaternary etch-stop layer comprises In x Ga 1-x As y P 1-y , where x and y are chosen based on chemical resistivity and barrier height.
4. The process according to claim 3 , wherein x is greater than or equal to 0.4 and less than or equal to 0.6.
5. The process according to claim 3 , wherein y is greater than zero and less than one.
6. The process according to claim 1 , wherein said first etch chemistry is H 2 SO 4 :H 2 O 2 :H 2 O.
7. The process according to claim 1 , further comprising:
depositing and patterning a gate metal layer in said gate region.
8. The process according to claim 1 , wherein said quaternary etch-stop layer has a thickness in a range from 10 Angstroms to 50 Angstroms.
9. The process according to claim 1 , further comprising:
opening a window in said first and said second contact layers; and
depositing a gate metal layer therein, said gate metal making electrical contact with said etch-stop layer.
10. A process for fabricating a field-effect transistor, the process comprising:
growing an epitaxial buffer layer of unintentionally doped gallium arsenide (GaAs) on a GaAs substrate;
growing an epitaxial n-channel layer on said buffer layer;
growing a barrier layer on said n-channel layer;
growing a quaternary etch-stop layer on said n-channel layer;
growing a first contact layer on said etch-stop layer;
growing a second contact layer of GaAs on said first contact layer; and
selectively etching said second contact layer to form a recess one surface and said first contact layer to form a gate region, wherein said selective etching is affected with a first etch chemistry, said first etch chemistry that etches said first and said second contact layers at a rate substantially faster than said first etch chemistry etches said quaternary etch-stop layer.
11. The process according to claim 10 , wherein said first etch chemistry etches said first and said second contact layers at a rate on the order of 150 times faster than said first etch chemistry etches said quaternary etch-stop layer.
12. The process according to claim 10 , wherein said quaternary etch-stop layer comprises In x Ga 1-x As y P 1-y , where x and y are chosen based on chemical resistivity and barrier height.
13. The process according to claim 12 , wherein x is greater than or equal to 0.4 and less than or equal to 0.6.
14. The process according to claim 12 , wherein y is greater than zero and less than one.
15. The process according to claim 10 , wherein said first etch chemistry is H 2 SO 4 :H 2 O 2 :H 2 O.
16. The process according to claim 10 , further comprising depositing a gate stack in said gate region.
17. The process according to claim 10 , wherein said quaternary etch-stop layer has a thickness in a range from 10 Angstroms to 50 Angstroms.