Wafer level photonic device die structure and method of making the same

1. A vertical Light Emitting diode (LED) device comprising:

a plurality of epi structures each including a first-type-doped portion, a second-type-doped portion, a quantum well structure between the first-type-doped and second-type doped portions, and an ohmic-reflector that is in electrical with the first-type-doped portion or the second-type-doped portion;

a semi-insulated carrier structure with a plurality of conductive contact pads in electrical contact with the epi structures and a plurality of bonding pads on a side of the carrier structure distal the epi structures, in which the conductive contact pads are in electrical communication with the bonding pads using at least one of vias and a Redistribution Layer (RDL), wherein each epi structure is disposed over a different one of the conductive contact pads;

a first insulating film on a side of the carrier structure proximal the epi structures; and

a second insulating film on a side of the carrier structure distal the epi structures.

2. The vertical LED device of claim 1 in which the first insulating film is disposed between the conductive contact pads and the carrier structure, and the second insulating film is disposed between the bonding pads and the carrier structure.

3. The vertical LED device of claim 1 , wherein at least a substantial majority of a bottom surface of each of the epi structures is in direct contact with the respective conductive contact pad.

4. The vertical LED device of claim 1 further comprising a phosphor coating on a side of the epi structures distal the carrier structure.

5. The vertical LED device of claim 1 in which each epi structure comprises a portion of a GaN wafer, and in which the carrier structure comprises at least one of a silicon wafer, a ceramic wafer, and a Metal Core Printed Circuit Board (MCPCB).

6. The vertical LED device of claim 1 comprising a single junction LED device.

7. The vertical LED device of claim 1 comprising a multi junction LED device.

8. the vertical LED device of claim 1 in which the epi structures each include an interconnect providing electrical contact between the first-type doped portion and the carrier structure, the interconnect comprising a Through GaN Via (TGV).

9. A semiconductor structure comprising:

an epi wafer; and

a carrier wafer with a plurality of conductive contact pads in electrical communication with the epi wafer, in which the epi wafer includes a first-type-doped portion and a second-type-doped portion and an ohmic reflector coupled to the second-type-doped portion, further in which the first-type-doped portion is distal the carrier wafer and in which the second-type-doped portion is proximal the carrier wafer.

10. The semiconductor structure of claim 9 in which each of the LED dies comprises:

a trench in the epi wafer making a first and a second epi portion, a second-type-doped part of the first portion in communication with a first-type-doped part of the second portion, thereby forming a multi junction LED device.

11. The semiconductor structure of claim 9 further comprising:

a wafer-level phosphor coating over the epi wafer.

12. The semiconductor structure of claim 9 in which each of the LED dies comprises:

a first trench and a second trench defining respective lateral die boundaries.

13. A wafer-level process for manufacturing a semiconductor structure that has an epi wafer coupled to a carrier wafer, the semiconductor structure having a plurality of Light Emitting diode (LED) dies, the process comprising for each of the dies:

forming a first contact pad on a second-type-doped portion of the epi wafer, the epi wafer also having a first-type-doped portion;

bonding the carrier wafer and the epi wafer so that the first contact pad electrically contacts a second contact pad on a side of the carrier wafer distal the epi wafer, the first contact pad electrically contacting the second contract pad by a first via through the carrier wafer; and

forming an interconnect through the epi wafer, the interconnect electrically coupling the first-type-doped portion to a third contact pad on the side of the carrier wafer distal the epi wafer.

14. The process of claim 13 in which interconnect electrically couples to the third contact pad by a second via through the carrier wafer.

15. the process of claim 13 further comprising:

applying a phosphor coating to the epi wafer.

16. The process of claim 15 further comprising:

dicing the semiconductor structure to separate the LED dies.

17. The process of claim 13 in which bonding the carrier wafer and the epi wafer comprises:

aligning the carrier wafer and the epi wafer using alignment marks placed on each of the carrier wafer and the epi wafer.

18. the process of claim 17 in which the aligning employs at least one of the following detection systems:

an infra-red detection system; and

a Charge Coupled Device (CCD) detection system.

19. The process of claim 13 in which the bonding comprises:

eutectically bonding the first contact pad to a fourth contact pad on the carrier wafer, the fourth contact pad in electrical contact with the first via.

20. The process of claim 13 further comprising for each of the dies:

separating a die from the wafer; and

surface mounting the die to a sub-mount using the second contact pad and the third contact pad.