Integrated circuit structure having selectively formed metal cap
Methods of forming an integrated circuit structure utilizing a selectively formed and at least partially oxidized metal cap over a gate, and associated structures. In one embodiment, a method includes providing a precursor structure including a transistor having a metal gate; forming an etch stop layer over an exposed portion of the metal gate; at least partially oxidizing the etch stop layer; and forming a dielectric layer over the at least partially oxidized etch stop layer.
1. A method of forming an integrated circuit structure, the method comprising:
providing a precursor structure including a transistor having a metal gate and spacers adjacent the metal gate;
forming an etch stop layer over an exposed portion of the metal gate,
wherein the etch stop layer is selectively formed over only the exposed portion of the metal gate as a metal layer,
wherein the metal layer includes iridium (Ir),
wherein the etch stop layer has a thickness of approximately 0.5 nanometers (nm);
at least partially oxidizing the etch stop layer; and
forming a dielectric layer over the at least partially oxidized etch stop layer.
2. The method of claim 1 , further comprising:
forming an opening in the dielectric layer extending to the etch stop layer; and
forming a contact in the opening.
3. The method of claim 2 , wherein the forming of the opening in the dielectric layer includes etching the dielectric layer, wherein the etch stop layer prevents etching of the metal gate during the etching, and wherein the etch stop layer physically and electrically isolates the metal gate from the contact after the forming of the contact.
4. The method of claim 1 , wherein the at least partially oxidizing of the etch stop layer includes oxidizing substantially an entirety of the etch stop layer.
5. The method of claim 1 , wherein the at least partially oxidizing of the etch stop layer includes oxidizing only an outer portion of the etch stop layer.
6. A method of forming an integrated circuit structure, the method comprising:
forming a transistor structure having:
an exposed metal gate;
a metal liner contacting the exposed metal gate;
a high-k liner surrounding the metal liner;
spacers abutting the high-k liner; and
a conductive layer below and alongside at least one of the spacers;
depositing an etch stop layer over only the exposed metal gate, the metal liner and the high-k liner, exclusive of the spacers,
wherein the etch stop layer is a metal including iridium (Ir), and
wherein the etch stop layer has a thickness of approximately 0.5 nanometers (nm);
oxidizing substantially an entirety of the etch stop layer;
forming a dielectric layer over the etch stop layer;
forming an opening in the dielectric layer extending to the etch stop layer and to the conductive layer; and
forming a contact to the conductive layer in the opening,
wherein the contact contacts the conductive layer, the at least one of the spacers and the etch stop layer.
7. The method of claim 6 , wherein the forming of the opening in the dielectric layer includes etching the dielectric layer to expose the conductive layer, and wherein the etch stop layer prevents etching of the metal gate during the etching, and wherein the etch stop layer physically and electrically isolates the metal gate from the contact after the forming of the contact.
8. The method of claim 6 , wherein the depositing of the etch stop layer includes depositing the etch stop layer over only the exposed metal gate, and is performed using chemical vapor deposition (CVD), atomic layer deposition (ALD) or electroless deposition.
9. The method of claim 5 , wherein the oxidized outer portion of the etch stop layer has a thickness of less than 0.5 nanometers.
10. The method of claim 6 , wherein the oxidized portion of the etch stop layer has a thickness of approximately 0.5 nanometers.