Method of fabricating semiconductor package
A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.
1. A method for fabricating a semiconductor package, comprising the steps of:
providing a mother substrate having a first face, a second face facing away the first face, a first circuit pattern formed in a respective first chip region included in a respective first chip group formed over the first face, and a second circuit pattern formed in a respective second chip region included in a respective second chip group formed over the second face;
attaching a first semiconductor chip to the first chip region such that the first semiconductor chip is electrically connected to the first circuit pattern;
attaching a second semiconductor chip to the second chip region such that the second semiconductor chip is electrically connected to the second circuit pattern, so a unit package comprising the mother substrate, the first semiconductor chip and the second semiconductor chip is formed;
covering the first and second semiconductor chips and fully filling between the first and second circuit patterns and the first and second semiconductor chips by disposing adhesive members over the first and second faces;
disposing cover substrates over the first and second faces by respectively covering the adhesive members disposed thereon to be fully filled between the unit package and the cover substrates by the adhesive members; and
forming a connection electrode passing through the mother substrate, the first and second circuit patterns, the adhesive members, and the cover substrates to electrically connect the first and second circuit patterns together.
2. The method according to claim 1 , wherein the first semiconductor chip and the first circuit pattern are electrically connected to a first bumps formed in the first semiconductor chip, and the second semiconductor chip and the second circuit pattern are electrically connected to a second bumps formed in the second semiconductor chip.
3. The method according to claim 1 , wherein the first semiconductor chip and the first circuit pattern are electrically connected to a first conductive wire, and the second semiconductor chip and the second circuit pattern are electrically connected to a second conductive wire.
4. The method according to claim 1 , wherein at least two mother substrates are stacked on each other.
5. The method according to claim 1 , wherein the first and second chip groups are formed over the mother substrate in a matrix shape, and the first and second chip groups are formed at substantially the same position in the mother substrate on the respective first and second face.
6. The method according to claim 1 , further comprising the step of: electrically connecting a connection member to the connection electrode exposed from one of the cover substrates after the step of forming the connection electrode.
7. The method according to claim 6 , further comprising the step of: forming a wiring over the cover substrate to electrically connect together the connection electrode to the connection member.
8. The method according to claim 1 , further comprising the step of: applying heat and pressure to the adhesive members wherein the step of applying is performed after the step of disposing the cover substrates over the adhesive members.
9. The method according to claim 1 , further comprising the steps of:
forming a third circuit pattern aligned with the first and second circuit patterns over one face of the at least one cover substrate;
mounting a third semiconductor chip onto the third circuit pattern; and
connecting the third circuit pattern to the connection electrode during the step of forming the connection electrode, wherein the steps of forming, mounting and connecting are performed before the step of disposing the cover substrates over the adhesive members.
10. The method according to claim 1 , further comprising the steps of:
inspecting the mother substrate to diagnose whether any first or second circuit pattern formed in any respective first or second chip region is faulty;
removing a portion of the mother substrate to form an opening in the mother substrate that corresponds to any first or second chip region that has a respective first or second circuit pattern which is diagnosed to be faulty; and
disposing a good substrate into the opening of the mother substrate,
wherein the steps of inspecting, removing and disposing are performed after the step of providing the mother substrate, and before the step of electrically connecting the first semiconductor chip to the first circuit pattern.
11. The method according to claim 10 , wherein the good substrate comprises a good first and second circuit patterns.
12. The method according to claim 1 , further comprising the steps of:
inspecting the mother substrate to diagnose whether any first or second circuit pattern formed in any respective first or second chip group is faulty;
removing a portion of the mother substrate to form an opening in the mother substrate corresponding to any first or second chip group that has a respective first or second circuit pattern which is diagnosed to be faulty; and
disposing a good substrate into the opening of the mother substrate,
wherein the steps of inspecting, removing and disposing are performed after the step of providing the mother substrate, and before the step of electrically connecting the first semiconductor chip to the first circuit pattern.
13. The method according to claim 12 , wherein the good substrate comprises a good first and second circuit patterns.
14. A method for fabricating a semiconductor package, comprising the steps of:
disposing a substrate, in which semiconductor chips are mounted on circuit patterns respectively disposed in a plurality of chip regions, into a plurality of openings formed in a mother substrate;
disposing adhesive members opposed to the respective semiconductor chips over the mother substrate;
disposing a cover substrate opposed to the semiconductor chip over the adhesive member; and
forming a connection electrode passing through the cover substrate, the mother substrate the first and second circuit patterns, the adhesive members, and electrically connected with the circuit pattern.
15. The method according to claim 14 , wherein the circuit pattern and the semiconductor chip are electrically connected together with a conductive wire.
16. The method according to claim 14 , wherein at least two mother substrates are stacked on each other.
17. The method according to claim 14 , further comprising the step of:
applying heat and pressure to the adhesive member wherein the applying heat and pressure step is performed after disposing the cover substrate over the adhesive member.
18. A method for fabricating a semiconductor package, comprising:
providing a mother substrate that comprises:
a plurality of first and second chip groups on respective opposing first and second faces of the mother substrate;
a plurality of first and second circuit regions in each respective first and second chip group; and
a plurality of first and second circuit patterns in each respective first and second circuit regions;
attaching a plurality of first and second semiconductor chips to respective first and second chip regions so that the first and second semiconductor chips are electrically coupled to respective first and second circuit patterns;
disposing adhesive members over the opposing first and second faces of the mother substrate to cover the first and second semiconductor chips and to fill in spaces between the first and second circuit patterns;
covering the adhesive members with cover substrates over the opposing first and second faces; and
connecting electrically the first and second circuit patterns together with connection electrodes that passes through the mother substrate, the first and second circuit patterns, the adhesive members, and through the cover substrates.
19. The method according to claim 18 , further comprising:
inspecting the mother substrate to diagnose whether any first or second circuit pattern formed in any respective first or second chip region is faulty;
removing a portion of the mother substrate to form an opening in the mother substrate that corresponds to any first or second chip region that has a respective first or second circuit pattern which is diagnosed to be faulty; and
disposing a good substrate into the opening of the mother substrate,
wherein the steps of removing and disposing performed after the step of providing the mother substrate, and before the step of electrically connecting the first semiconductor chip to the first circuit pattern.
20. The method according to claim 18 , further comprising the steps of:
inspecting the mother substrate to diagnose whether any first or second circuit pattern formed in any respective first or second chip group is faulty;
removing a portion of the mother substrate corresponding to form an opening in the mother substrate that corresponds to any first or second chip group that has a respective first or second circuit pattern which is diagnosed to be faulty; and
disposing a good substrate into the opening of the mother substrate,
wherein the steps of removing and disposing are performed after the step of providing the mother substrate, and before the step of electrically connecting the first semiconductor chip to the first circuit pattern.