Circuit for generating a clock signal for interleaved PFC stages and method thereof

1. A method for generating a clock signal for an oscillator of a switched mode power supply operating in at least one of a discontinuous conduction mode (DCM) or a critical conduction mode (CRM), comprising:

discharging an energy storage element from a first level;

generating a synchronization signal in accordance with a voltage across the energy storage element, the synchronization signal having a first frequency;

generating a first signal from the synchronization signal, the first signal having a second frequency;

generating a second signal from the first signal, the second signal having the second frequency; and

using the synchronization signal and one of the first and second signals having the second frequency to generate a first clock signal.

2. The method of claim 1 , further including using the synchronization signal and another of the first and second signals having the second frequency to generate a second clock signal.

3. The method of claim 2 , further including charging the energy storage element using a first current source and discharging the energy storage element using a second current source.

4. The method of claim 3 , wherein a discharge current level of the second current source is less than a discharge current level of the first current source.

5. The method of claim 1 , wherein generating the synchronization signal includes comparing a voltage level across the energy storage element with a reference voltage.

6. The method of claim 1 , wherein using the synchronization signal and the one of the first and second signals having the second frequency to generate the first clock signal includes:

generating a set signal of a first latch from the synchronization signal and the one of the first and second signals having the second frequency;

setting an output signal of the first latch; and

forming the first clock signal using the output signal of the first latch.

7. The method of claim 6 , further including resetting the output signal of the first latch.

8. The method of claim 6 , further including:

generating a set signal of a second latch from the synchronization signal and another of the first and second signals having the second frequency;

setting an output signal of the second latch; and

forming a second clock signal using the output signal of the second latch.

9. A switched mode power supply operating in DCM or in CRM having a clock generation circuit that includes an oscillator, comprises:

a comparison circuit having first and second inputs and an output;

a divider circuit having an input and an output, the input coupled to the output of the comparison circuit;

a first logic gate having first and second inputs and an output, the first input coupled to the output of the comparison circuit, the second input coupled to the output of the divider circuit; and

a first latch having an input coupled to the output of the first logic gate, an input coupled to a first driver circuit, and an output coupled to an input of a second logic gate.

10. The switched mode power supply of claim 9 , further including:

a third logic gate having first and second inputs and an output, the first input coupled to the output of the comparison circuit, the second input coupled to the output of the divider circuit; and

a second latch having an input coupled to the output of the third logic gate, an input coupled to a second driver circuit, and an output coupled to an input of a fourth logic gate.

11. The switched mode power supply of claim 9 , further including

a first switch having first and second current conducting terminals and a control terminal, the first current conducting terminal connected to the first input of the comparison circuit and the control terminal of the switch coupled to an output of the comparison circuit; and

a first current source coupled to the second current conducting terminal of the first switch.