SONOS FLASH MEMORY DEVICE
A semiconductor device fabricated by forming a dummy layer on a semiconductor substrate, forming a groove in the semiconductor substrate while using the dummy layer as a mask, forming a tunnel insulating film and a trap layer to cover an inner surface of the groove and the dummy layer, eliminating the trap layer formed above the upper surface and at the sides of the dummy layer, and forming a top insulating film to cover a remaining trap layer and the exposed tunnel insulating film.
1 . A system, comprising:
a processor;
a cache;
a user input component; and
a flash memory, wherein the flash memory comprises:
a substrate;
a dummy layer formed on the substrate;
a groove formed in the substrate, the groove being formed while using the dummy layer as a mask;
a tunnel insulating film and a trap layer disposed on an inner surface of the groove and the dummy layer;
a top insulating film covering portions of the trap layer and tunnel insulating film,
wherein the trap layer is covered by the top insulating film to suppress erosion of the trap layer.
2 . The system according to claim 1 , wherein portions of the trap layer not covered by the top insulating film are eliminated during fabrication of the flash memory.
3 . The system according to claim 2 , wherein the portions of the trap layer are eliminated by forming a bury layer in the groove to expose the trap layer at the sides of the dummy layer and eliminating the trap layer while using the bury layer as a mask.
4 . The system according to claim 3 , wherein forming a bury layer during the fabricating of the flash memory comprises:
forming a layer to be formed as the bury layer to fill the groove and to cover the trap layer; and
eliminating the layer to be formed as the bury layer to expose at least the trap layer at the sides of the dummy layer.
5 . The system according to claim 1 , wherein the dummy layer of the flash memory is eliminated.
6 . The system according to claim 5 , wherein the flash memory further comprises a bit line disposed in the substrate where the dummy layer has been eliminated.
7 . The system according to claim 6 , wherein the flash memory further comprises a gate electrode formed in a groove in the top insulating film.
8 . The system according to claim 7 , wherein the bit line is disposed in the substrate by performing an ion implantation in the semiconductor substrate while using the gate electrode as a mask.
9 . The according to claim 8 , wherein the gate electrode is formed in the flash memory by filling the groove and covering the top insulating film to form a layer to be formed as the gate electrode, and polishing the layer to be formed as the gate electrode to be flush with the dummy layer.
10 . The system according to claim 8 , wherein the flash memory further comprises an insulating layer disposed on the bit line to expose an upper surface of the gate electrode.
11 . The system according to claim 10 , wherein the flash memory further comprises a word line coupled to the gate electrode and intersecting with the bit line.
12 . The system according to claim 6 , further comprising a metal silicide layer disposed on the bit line between the grooves where the dummy layer has been eliminated.
13 . The system according to claim 1 , wherein the dummy layer and the trap layer are formed from a same material.
14 . The system according to claim 1 , wherein a silicon nitride is used for forming the dummy layer and the trap layer.
15 . The system according to claim 1 wherein the system is a portable media player.
16 . The system according to claim 1 wherein the system is a cellular telephone.
17 . The system according to claim 1 wherein the system is a computing device.
18 . The system according to claim 17 wherein the computing device is a desktop computing device.
19 . The system according to claim 17 wherein the computing device is a laptop or mobile computing device.
20 . The system according to claim 1 wherein the system is a video game console device.