Edge termination by ion implantation in GaN
View Patent ↗An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.
1. An edge terminated semiconductor device, comprising;
a GaN substrate;
a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region having a resistivity that is at least 90% of maximum achieveable resistivity;
an insulating layer disposed over the ion-implanted insulation region; and
a conductive layer disposed over the GaN epitaxial layer, at least a portion of the ion-implanted insulation region, and at least a portion of the insulating layer.
2. An edge terminated semiconductor device, comprising;
a GaN substrate;
a doped GaN epitaxial layer deposited on the GaN substrate including an ion-implanted insulation region, wherein the ion of the ion-implanted region is selected from the group consisting of helium, argon, nitrogen, and combinations thereof;
an insulating layer disposed over the ion-implanted insulation region; and
a conductive layer disposed over the GaN epitaxial layer, at least a portion of the ion-implanted insulation region, and at least a portion of the insulating layer.
3. An edge terminated semiconductor device, comprising;
a GaN substrate;
a doped GaN epitaxial layer deposited on the GaN substrate including an ion-implanted insulation region, wherein the ions are implanted to a depth of at least 450 nm;
an insulating layer disposed over the ion-implanted insulation region; and
a conductive layer disposed over the GaN epitaxial layer, at least a portion of the ion-implanted insulation region, and at least a portion of the insulating layer.
4. The device of claim 1 , wherein the ion-implanted insulation region has a depth of at least 450 nm.
5. The device of claim 1 or 2 , wherein the ion-implanted insulation region has a resistivity greater than 10 10 ohm-sq.
6. The device of claim 1 , wherein the GaN epitaxy layer is n-doped.
7. The device of claim 1 , wherein the mean ion-implanted ion concentration is >10 18 cm −3 .
8. The device of claim 1 , wherein the ion-implanted insulation region comprises a distribution of implanted ions.
9. The device of claim 1 , wherein the conductive layer comprises a Schottky metal.
10. The device of claim 9 , wherein the Schottky metal is selected from the group consisting of nickel, platinum, palladium and gold and combinations thereof.
11. The device of claim 1 , wherein the conductive layer comprises p+GaN.
12. The device of claim 1 , wherein an overlap between the conductive layer and the ion-implanted insulation region is about 0.5 μm to about 10 μm.
13. The device of claim 2 , wherein the implant ion comprises nitrogen.
14. The device of claim 1 , 2 or 3 wherein the insulating layer is deposited on the at least a portion of the ion-implanted insulation region.
15. The device of claim 11 , wherein the device is a diode.
16. The device of claim 15 , wherein the diode is selected from the group of p-n diodes, PiN diodes, and merged PiN-Schottky diodes.
17. The device of claim 11 , wherein the device is a field effect transistor.
18. The device of claim 17 , wherein the field effect transistor is a vertical junction field effect transistor.