Granted Patent B2

US 8,558,242 · App. 13/315,705 · Granted Oct 15, 2013

Abstract

Claims (47)

1. A semiconductor structure comprising:

a III-nitride substrate having a top surface and an opposing bottom surface;

a first III-nitride layer of a first conductivity type coupled to the top surface of the III-nitride substrate;

a second III-nitride layer of a second conductivity type coupled to the first III-nitride layer along a vertical direction;

a third III-nitride layer of a third conductivity type coupled to the second III-nitride layer along the vertical direction;

a first trench extending through a portion of the third III-nitride layer to the first III-nitride layer;

a second trench extending through another portion of the third III-nitride layer to the second III-nitride layer;

a first metal layer coupled to the second and the third III-nitride layers; and

a second metal layer coupled to the bottom surface of the III-nitride substrate.

2. The semiconductor structure of claim 1 wherein a sidewall of each of the first trench and the second trench is lined by a layer of dielectric material.

3. The semiconductor structure of claim 1 wherein a thickness of the second III-nitride layer ranges from about 100 nanometers to about 2,000 nanometers.

4. The semiconductor structure of claim 1 wherein the second III-nitride layer comprises one of AlGaN or InGaN.

5. The semiconductor structure of claim 1 wherein the third III-nitride layer is characterized by a thickness of up to 500 nanometers.

6. The semiconductor structure of claim 1 wherein a dopant concentration of the third III-nitride layer is between 1×10 18 cm −3 and 1×10 20 cm −3 .

7. A vertical III-nitride field effect transistor comprising:

a drain comprising an n + type material;

a drain contact electrically coupled to the drain;

a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction;

a channel region comprising a third III-nitride material coupled to the drift region;

a gate region coupled to the channel region;

a gate contact electrically coupled to the gate region;

a source coupled to the channel region; and

a source contact electrically coupled to the source;

wherein the channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction from the source to the drain via the drift region.

8. The vertical III-nitride field effect transistor of claim 7 wherein the second III-nitride material comprises an n − type GaN epitaxial layer having a dopant concentration less than or equal to a dopant concentration of the n + type material.

9. The vertical III-nitride field effect transistor of claim 7 wherein the channel region comprises a p-type III-nitride material.

10. The vertical III-nitride field effect transistor of claim 7 wherein the source comprises a III-nitride material having an n + type.

11. A method comprising:

providing a III-nitride substrate having a top surface and an opposing bottom surface;

forming a first III-nitride epitaxial layer over the top surface of the III-nitride substrate, wherein the first III-nitride epitaxial layer is characterized by a first conductivity;

forming a second III-nitride epitaxial layer over the first III-nitride layer, wherein the second III-nitride epitaxial layer is characterized by a second conductivity opposite of the first conductivity;

forming a third III-nitride epitaxial layer over the second III-nitride layer, wherein the third III-nitride epitaxial layer is characterized by a third conductivity;

removing a portion of the third III-nitride epitaxial layer and the second III-nitride epitaxial layer to form a first trench extending through a thickness of the third III-nitride epitaxial layer and further protruding into the second III-nitride epitaxial layer;

removing another portion of the third III-nitride epitaxial layer, the second III-nitride epitaxial layer, and a portion of the first III-nitride epitaxial layer to form a second trench extending through the thickness of the third III-nitride epitaxial layer, through a thickness of the second III-nitride material, and further protruding into the first III-nitride epitaxial layer;

forming a dielectric layer over the third III-nitride epitaxial layer;

forming a first metallic structure electrically coupled to the third III-nitride layer;

forming a second metallic structure electrically coupled to the second III-nitride layer; and

forming a metal structure overlying the dielectric layer, wherein the metal structure is electrically coupled to the third III-nitride layer via the first metallic structure and to the second III-nitride layer via the second metallic structure.

12. The method of claim 11 wherein the dielectric layer lines inner walls of the first trench and the second trench.

13. The method of claim 11 further comprising forming a third metallic structure electrically coupled to the III-nitride substrate.

14. The method of claim 11 wherein the first III-nitride epitaxial layer is characterized by a thickness ranging from about 5 μm an to about 100 μm.

15. The method of claim 11 wherein the second III-nitride epitaxial layer is characterized by a thickness ranging from about 100 nm to 1,000 nm.

16. The method of claim 11 wherein the first III-nitride epitaxial layer comprises an n-type GaN layer.

17. The method of claim 11 wherein the third conductivity is same as the first conductivity.

18. The method of claim 11 wherein forming the dielectric layer comprises performing at least one of an Metal-Organic Chemical Vapor Deposition (MOCVD) process or an Atomic Layer Deposition (ALD) process.

19. The method of claim 11 wherein the metal structure fills the first trench and the second trench and a first portion of the metal structure is electrically coupled to the third III-nitride epitaxial layer and a second portion of the metal structure is electrically coupled to the second III-nitride epitaxial layer.

20. The method of claim 11 wherein the dielectric layer comprises at least one of silicon dioxide, silicon oxynitride, silicon gallium nitride, silicon aluminum nitride, aluminum gallium nitride, or aluminum nitride.

Assignments (11)