Integrated circuit packaging system with terminals and method of manufacture thereof

1. A method of manufacture of an integrated circuit packaging system comprising:

forming a lower interior conductive layer directly on a carrier having an exterior conductive layer, the lower interior conductive layer on a side of the carrier opposite from the exterior conductive layer, and the lower interior conductive layer having a lower layer top side;

forming an interior insulation layer directly on the lower interior conductive layer, the lower interior conductive layer within the interior insulation layer, and the lower layer top side of the lower interior conductive layer coplanar with an interior insulation bottom side of the interior insulation layer;

removing a portion of the carrier to form a lead having a lead top side wider than a lead bottom side, the lead for conducting electrical signals, and the lead top side coplanar with the lower layer top side of the lower interior conductive layer with the lead having a curved surface extending from the lead top side to the lead bottom side;

forming a protection layer directly on a bottom side of the lower interior conductive layer, a lead non-horizontal side, the exterior conductive layer, and a bottom extent of the interior insulation layer, the protection layer coplanar with a lead top side;

forming an upper interior conductive layer directly on the interior insulation layer, the upper interior conductive layer having an upper contact for attaching an internal connector;

mounting an integrated circuit over the upper interior conductive layer, the integrated circuit attached to the upper contact with the internal connector; and

forming an encapsulation over the integrated circuit, the internal connector, and the upper interior conductive layer to hermetically seal the integrated circuit for environmental protection.

2. The method as claimed in claim 1 wherein mounting the integrated circuit includes mounting the integrated circuit directly over the lead.

3. The method as claimed in claim 1 further comprising:

forming a package paddle adjacent the lead; and

wherein:

forming the lower interior conductive layer includes forming the lower interior conductive layer directly on the package paddle.

4. The method as claimed in claim 1 wherein:

forming the lead includes forming the lead having a lead step portion; and

forming the lower interior conductive layer includes forming the lower interior conductive layer directly on the lead step portion.

5. The method as claimed in claim 1 further comprising forming a conductive cap directly on the lead top side.

6. A method of manufacture of an integrated circuit packaging system comprising:

forming a lower interior conductive layer directly on a carrier having an exterior conductive layer, the lower interior conductive layer on a side of the carrier opposite from the exterior conductive layer, and the lower interior conductive layer having a lower layer top side;

forming an interior insulation layer directly on the lower interior conductive layer;

removing a portion of the carrier to form a lead having a lead top side wider than lead bottom side, the lead for conducting electrical signals, and the lead top side coplanar with the lower layer top side of the lower interior conductive layer with a non-horizontal side of the lead extending from the lead top side to the lead bottom side;

forming an upper interior conductive layer directly on the interior insulation layer, the upper interior conductive layer having an upper contact for attaching an internal connector, the lower interior conductive layer within the interior insulation layer, and the lower layer top side of the lower interior conductive layer coplanar with an interior insulation bottom side of the interior insulation layer and the lead top side;

mounting an integrated circuit over the upper interior conductive layer, the integrated circuit attached to the upper contact with the internal connector;

forming a protection layer directly on a bottom side of the lower interior conductive layer, a lead non-horizontal side, the exterior conductive layer, and a bottom extent of the interior insulation layer, the protection layer coplanar with a lead top side; and

forming an encapsulation over the integrated circuit, the internal connector, and the upper interior conductive layer to hermetically seal the integrated circuit for environmental protection.

7. The method as claimed in claim 6 further comprising:

forming a package paddle adjacent the lead; and

attaching an attach layer to the package paddle and the integrated circuit.

8. The method as claimed in claim 6 further comprising attaching an internal connector to the integrated circuit and the lower interior conductive layer.

9. The method as claimed in claim 6 further comprising attaching an attach layer to the integrated circuit and the lower interior conductive layer.

10. The method as claimed in claim 6 wherein mounting the integrated circuit includes mounting a flip chip over the upper interior conductive layer.

11. An integrated circuit packaging system comprising:

a lower interior conductive layer directly on a lead top side, the lower interior conductive layer having a lower layer top side;

an interior insulation layer directly on the lower interior conductive layer, the lower interior conductive layer within the interior insulation layer, and the lower layer top side of the lower interior conductive layer coplanar with an interior insulation bottom side of the interior insulation layer and the lead top side;

a lead having a lead top side wider than a lead bottom side, the lead for conducting electrical signals, and the lead top side coplanar with the lower layer top side of the lower interior conductive layer with the lead having a curved surface extending from the lead top side to the lead bottom side;

an exterior conductive layer directly on the lead bottom side;

a protection layer directly on a bottom side of the lower interior conductive layer, a lead non-horizontal side, the exterior conductive laver, and a bottom extent of the interior insulation layer, the protection layer coplanar with a lead top side;

an upper interior conductive layer directly on the interior insulation layer, the upper interior conductive layer having an upper contact for attaching an internal connector;

an integrated circuit over the upper interior conductive layer, the integrated circuit attached to the upper contact with the internal connector; and

an encapsulation over the integrated circuit, the internal connector, and the upper interior conductive layer to hermetically seal the integrated circuit for environmental protection.

12. The system as claimed in claim 11 wherein the integrated circuit is directly over the lead.

13. The system as claimed in claim 11 further comprising:

a package paddle adjacent the lead; and

wherein:

the lower interior conductive layer is directly on the package paddle.

14. The system as claimed in claim 11 wherein:

the lead includes a lead step portion; and

the lower interior conductive layer is directly on the lead step portion.

15. The system as claimed in claim 11 further comprising a conductive cap directly on the lead top side.

16. The system as claimed in claim 11 wherein the lower interior conductive layer is within the interior insulation layer and the lower layer top side of the lower interior conductive layer coplanar with an interior insulation bottom side of the interior insulation layer and the lead top side.

17. The system as claimed in claim 16 further comprising:

a package paddle adjacent the lead; and

an attach layer attached to the package paddle and the integrated circuit.

18. The system as claimed in claim 16 further comprising an internal connector attached to the integrated circuit and the lower interior conductive layer.

19. The system as claimed in claim 16 further comprising an attach layer attached to the integrated circuit and the lower interior conductive layer.

20. The system as claimed in claim 16 wherein the integrated circuit is a flip chip over the upper interior conductive layer.