Hybrid CMOS nanowire mesh device and PDSOI device
View Patent ↗A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate.
1. A method of forming a hybrid semiconductor structure comprising:
providing a semiconductor on insulator substrate comprising a top semiconductor layer and a buried insulating layer;
providing a material stack on top of the top semiconductor layer, the material stack including alternating layers of semiconductor material and sacrificial material, wherein the bottommost layer of the patterned material stack is the top semiconductor layer of the semiconductor on insulator substrate;
providing a hard mask over the patterned material stack;
blocking the hard mask and material stack in a first portion of the semiconductor structure;
removing the hard mask and material stack in a second portion of the semiconductor structure while leaving a layer of the top semiconductor layer;
regrowing the layer of the top semiconductor layer into a thicker layer of the top semiconductor layer in the second portion of the semiconductor structure to form a partially depleted semiconductor on insulator (PDSOI) layer;
patterning the hard mask to form a plurality of hard mask structures in the first portion of the semiconductor structure;
forming a dummy gate over a central portion of each of said plurality of hard mask structures in the first portion of the semiconductor structure and over a central portion of the PDSOI layer in the second portion of the semiconductor structure;
forming a sacrificial material layer abutting the dummy gates in the first and second portions of the semiconductor structure;
removing the dummy gates to form a trench in the sacrificial material layer of each of the first and second portions of the semiconductor structure to expose the central portion of each of said plurality of hard mask structures in the first portion of the semiconductor structure and the central portion of the PDSOI layer in the second portion of the semiconductor structure;
blocking the second portion of the semiconductor structure;
etching a plurality of fins within the trench in the patterned material stack in the first portion of the semiconductor structure using the plurality of patterned hard masks as an etch mask;
removing the plurality of patterned hard masks in the first portion of the semiconductor structure;
removing each layer of sacrificial material within the trench in the first portion of the semiconductor structure to form a plurality of vertically stacked and vertically spaced apart semiconductor nanowires within the trench in the first portion of the semiconductor structure; and
filling the trenches in the first and second portions of the semiconductor structure with a gate region.
2. The method of claim 1 wherein the PDSOI layer has a thickness of 5 to 200 nm.
3. The method of claim 2 wherein the top semiconductor layer in the second portion is thicker than the top semiconductor layer in the first portion.
4. The method of claim 1 wherein between removing the plurality of patterned hard masks and removing each layer of sacrificial material, further comprising forming a spacer within the trenches of the first and second portions of the semiconductor structure.
5. The method of claim 1 wherein said removing each layer of sacrificial material is performed by chemically utilizing an etchant that exploits the lower oxidation potential of the layers of sacrificial material compared to the layers of semiconductor material.
6. The method of claim 1 wherein said removing each layer of sacrificial material is performed by utilizing a plasma etching process.
7. The method of claim 1 wherein said removing each layer of sacrificial material is performed using a wet or dry oxidation process.
8. The method of claim 1 wherein each semiconductor nanowire has a pitch of less than 200 nm and a width of less than 40 nm.
9. The method of claim 1 wherein a nanowire mesh device is formed in the first portion of the semiconductor structure and a PDSOI device is formed in a second portion of the semiconductor structure.
10. The method of claim 1 wherein a plurality of nanowire mesh devices are formed in the first portion of the semiconductor structure and a plurality of PDSOI devices are formed in a second portion of the semiconductor structure.
11. The method of claim 10 wherein the semiconductor structure is an integrated circuit.