Storing data in parallel in a flash storage device using on chip page shifting between planes

1. A method for storing data in a flash storage device, the method comprising:

in a flash storage device having a controller and a memory in communication with the controller, the memory including a plurality of planes, each of the planes having a sequence of pages:

receiving data;

iteratively writing portions of the data in parallel into a page in each of the plurality of planes;

reading the pages in each of the planes, at least some of the pages read in parallel being in a different respective page of the sequence of pages in the respective plane;

determining, for at least one of the pages read, whether to shift pages from an initial plane to a different one of the planes; and

storing the data in the memory based on the determined shift,

wherein the determined shift and the storage of the data result in a sequential ordering of data within the numbered sequence of pages in at least one of the planes.

2. The method of claim 1 , wherein the plurality of planes comprise “N” number of planes;

wherein the portions of the data comprise “N” pages of the data;

wherein iteratively writing the “N” pages of data in parallel comprises:

writing the first “N” pages of data in parallel in a first sequence across the “N” number of planes; and

writing subsequent pages of data in parallel in a sequence across the “N” number of planes that is different from the first sequence.

3. The method of claim 2 , wherein iteratively writing the “N” pages of data in parallel further comprises, for each iteration, shifting a predetermined number of planes to begin the “N” pages of data.

4. The method of claim 1 , wherein reading the pages in each of the planes comprises:

reading a page from each of the plurality of planes in parallel, the page read from each of the plurality of planes in a different one of the sequence of pages.

5. The method of claim 4 , wherein the memory includes single level cell memory with N planes;

wherein iteratively writing portions of the data in parallel into a page in each of the plurality of planes comprises writing the data in the N pages of each of the N planes;

wherein reading in parallel the N pages in each of the N planes comprises:

reading N pages in parallel from each of the N planes N times such that:

in a first parallel reading, reading the first page of the first of the N planes, reading the second page of the second of the N planes, reading the third page of the third of the N planes, and continuing the sequence of reading until the Nth page is read from the Nth of the N planes;

in a second parallel reading, reading from the Nth page of the first of the N planes, reading the first page of the second of the N planes, reading the second page of the third of the N planes, and continuing the sequence of reading until the Nth−1 page is read from the Nth of the N planes;

in a third parallel reading, reading from the Nth−1 page of the first of the N planes, reading the Nth page of the second of the N planes, reading the first page of the third of the N planes, and continuing the sequence of reading until the Nth−2 page is read from the Nth of the N planes; and

continuing the sequence of parallel readings until the Nth parallel reading, which includes reading the second page of the first of the N planes, reading the third page of the second of the N planes, reading the fourth page of the third of the N planes, and

continuing the sequence of reading until the first page is read from the Nth of the N planes.

6. The method of claim 5 , wherein determining whether to shift pages from an initial plane to a different one of the planes comprises:

performing no reordering of the first page in each of the N planes;

performing a reordering using at least one page shift register such that the second page in each of the N planes is shifted the equivalent of one position left so that data stored in the second page in the first of the N planes is moved to the second page in the Nth of the N planes, data stored in the second page in the second of the N planes is moved to the second page in the first of the N planes, data stored in the second page in the third of the N planes is moved to the second page in the second of the N planes;

performing a reordering using the at least one page shift register such that the third page in each of the N planes is shifted the equivalent of two positions left; and

iteratively performing, until the Nth page, a reordering using the at least one page shift register such that the Xth page in each of the N planes is shifted the equivalent of Xth−1 positions left.

7. The method of claim 1 , wherein the determined shift and the storage of the data result in a sequential ordering of data within the numbered sequence of pages in all of the planes.

8. The method of claim 7 , wherein the memory includes single level cell memory with N planes and M pages in each of the planes;

wherein the memory includes multi-level cell memory with N planes and M pages in each of the planes;

wherein iteratively writing portions of the data in parallel into a page in each of the plurality of planes comprises iteratively writing the portions of the data in parallel to a page in single level cell memory in each of the N planes; and

wherein storing the data in the memory based on the determined shift comprises storing the data in parallel in the multi-level cell memory so that the first plane includes pages 0 through M−1, the second plane includes pages M through 2M−1, the third plane includes pages 2M through 3M−1, and continuing the sequence of the planes with the Nth page including pages (N−1)×M page through N×M−1 page.

9. The method of claim 8 , wherein N=M.

10. The method of claim 8 , further comprising shifting at least some of the pages in response to determining whether to shift the pages; and

wherein storing the data in the memory based on the determined shift comprises storing the shifted pages into multi-level cell memory.

11. The method of claim 1 , wherein iteratively writing portions of the data in parallel into a page in each of the plurality of planes comprises iteratively writing the portions of the data into single level cell memory;

further comprising shifting at least some of the pages in response to determining whether to shift the pages; and

wherein storing the data in the memory based on the determined shift comprises storing the shifted pages into multi-level cell memory.

12. A flash memory device configured to store data, the flash memory device comprising:

a memory including a plurality of planes, each of the planes having a sequence of pages; and

a controller in communication with the memory, the controller is configured to:

receive data;

iteratively write portions of the data in parallel into a page in each of the plurality of planes;

read the pages in each of the planes, at least some of the pages read in parallel being in a different respective page of the sequence of pages in the respective plane;

determine, for at least one of the pages read in parallel, whether to shift pages from an initial plane to a different one of the planes; and

store the data in the memory based on the determined shift,

wherein the determined shift and the storage of the data result in a sequential ordering of data within the numbered sequence of pages in at least one of the planes.

13. The flash memory device of claim 12 , wherein the plurality of planes comprise “N” number of planes;

wherein the portions of the data comprise “N” pages of the data;

wherein the controller is configured to iteratively write the “N” pages of data in parallel by:

writing the first “N” pages of data in parallel in a first sequence across the “N” number of planes; and

writing subsequent pages of data in parallel in a sequence across the “N” number of planes that is different from the first sequence.

14. The flash memory device of claim 13 , wherein the controller is configured to iteratively write the “N” pages of data in parallel by, for each iteration, shifting a predetermined number of planes to begin the “N” pages of data.

15. The flash memory device of claim 12 , wherein the controller is configured to read in parallel the pages in each of the planes by:

reading a page from each of the plurality of planes in parallel, the page read from each of the plurality of planes in a different one of the sequence of pages.

16. The flash memory device of claim 15 , wherein the memory includes single level cell memory with N planes;

wherein the controller is configured to iteratively write portions of the data in parallel into a page in each of the plurality of planes by writing the data in the N pages of each of the N planes;

wherein the controller is configured to read in parallel the N pages in each of the N planes by:

reading N pages in parallel from each of the N planes N times such that:

in a first parallel reading, reading the first page of the first of the N planes, reading the second page of the second of the N planes, reading the third page of the third of the N planes, and continuing the sequence of reading until the Nth page is read from the Nth of the N planes;

in a second parallel reading, reading from the Nth page of the first of the N planes, reading the first page of the second of the N planes, reading the second page of the third of the N planes, and continuing the sequence of reading until the Nth−1 page is read from the Nth of the N planes;

in a third parallel reading, reading from the Nth−1 page of the first of the N planes, reading the Nth page of the second of the N planes, reading the first page of the third of the N planes, and continuing the sequence of reading until the Nth−2 page is read from the Nth of the N planes; and

continuing the sequence of parallel readings until the Nth parallel reading, which includes reading the second page of the first of the N planes, reading the third page of the second of the N planes, reading the fourth page of the third of the N planes, and continuing the sequence of reading until the first page is read from the Nth of the N planes.

17. The flash memory device of claim 16 , further comprising at least one page shift register; and

wherein the controller is configured to determine whether to shift pages from an initial plane to a different one of the planes by:

performing no reordering of the first page in each of the N planes;

performing a reordering using the at least one page shift register such that the second page in each of the N planes is shifted the equivalent of one position left so that data stored in the second page in the first of the N planes is moved to the second page in the Nth of the N planes, data stored in the second page in the second of the N planes is moved to the second page in the first of the N planes, data stored in the second page in the third of the N planes is moved to the second page in the second of the N planes;

performing a reordering using the at least one page shift register such that the third page in each of the N planes is shifted the equivalent of two positions left; and

iteratively performing, until the Nth page, a reordering using the at least one page shift register such that the Xth page in each of the N planes is shifted the equivalent of Xth−1 positions left.

18. The flash memory device of claim 12 , wherein the determined shift and the storage of the data result in a sequential ordering of data within the numbered sequence of pages in all of the planes.

19. The flash memory device of claim 18 , wherein the memory includes single level cell memory with N planes and M pages in each of the planes;

wherein the memory includes multi-level cell memory with N planes and M pages in each of the planes;

wherein the controller is configured to iteratively write portions of the data in parallel into a page in each of the plurality of planes by iteratively writing the portions of the data in parallel to a page in single level cell memory in each of the N planes; and

wherein the controller is configured to store the data in the memory based on the determined shift by storing the data in parallel in the multi-level cell memory so that the first plane includes pages 0 through M−1, the second plane includes pages M through 2M−1, the third plane includes pages 2M through 3M−1, and continuing the sequence of the planes with the Nth page including pages (N−1)×M page through N×M−1 page.

20. The flash memory device of claim 19 , wherein the controller is further configured to shift at least some of the pages in response to determining whether to shift the pages; and

wherein the controller is configured to store the data in the memory based on the determined shift by storing the shifted pages into multi-level cell memory.

21. The flash memory device of claim 12 , wherein the controller is configured to iteratively write portions of the data in parallel into a page in each of the plurality of planes by iteratively writing the portions of the data into single level cell memory;

wherein the controller is further configured to shift at least some of the pages in response to determining whether to shift the pages; and

wherein the controller is configured to store the data in the memory based on the determined shift by storing the shifted pages into multi-level cell memory.