System and method for pre-interleaving sequential data

1. A method of loading data from a host system into a memory device, the method comprising:

performing in the host system:

accessing a programming indicator, the programming indicator indicative of a parallel plane structure of multiple planes in different dies for writing the data to the memory device in a programming mode, wherein the memory device includes a different parallel plane structure for writing the data to the memory device in a normal mode;

identifying a sequential stream of data for transmission to the memory device, wherein the sequential stream comprises a finite series of sections of data in sequential order;

using the programming indicator and the identified sequential stream of data in order to obtain interleaved data, the interleaved data comprising a reordering of the sequential stream of data conforming to the parallel plane structure of the multiple planes in the different dies such that the interleaved data comprises sequential data, according to the sequential order of the sequential stream of data, across the multiple planes within the dies and non-sequential data, according to the sequential order of the sequential stream of data, for the multiple planes across the different dies in order for the memory device to write the interleaved data in parallel in the programming mode; and

sending the interleaved data sequentially to the memory device such that the memory device stores the sequential data, according to the sequential order of the sequential stream of data, across the multiple planes within the dies and the non-sequential data, according to the sequential order of the sequential stream of data, for the multiple planes across the different dies.

2. The method of claim 1 , wherein using the programming indicator and the identified sequential stream of data in order to obtain interleaved data comprises:

accessing a memory location using the programming indicator and the identified sequential stream of data in order to obtain the interleaved data.

3. The method of claim 1 , wherein using the programming indicator and the identified sequential stream of data in order to obtain interleaved data comprises:

accessing the sequential stream of data; and

reordering the sequential stream of data using the programming indicator in order to generate the interleaved data.

4. The method of claim 1 , wherein the programming indicator comprises a type of the memory device; and

further comprising using a data construct to correlate the type of the memory device to a particular parallel plane structure.

5. The method of claim 1 , further comprising sending a communication to the memory device, the communication indicative of the programming mode to the memory device in order for the memory device to configure itself to program the interleaved data in the multiple pages across the different dies in parallel according to the programming mode.

6. The method of claim 5 , wherein the sequential stream of data comprises a sequential stream of pages;

wherein the different dies comprise a first die and a second die; and

wherein the sequential stream of pages is reordered into the interleaved data such that after the memory device programs the interleaved data in multiple pages across the multiple dies according to the programming mode, the first die and the second die including stored pages in a sequence identical to the sequential stream of pages.

7. The method of claim 5 , further comprising sending a second communication to the memory device, the second communication indicative of the normal mode to the memory device in order for the memory device to configure itself to program in a metablock size, the metablock size being smaller than a size of the multiple pages across the different dies in the programming mode.

8. The method of claim 7 , wherein the metablock size consists of pages in a single die.

9. The method of claim 1 , wherein accessing the programming indicator is in response to a query to the memory device for the parallel plane structure of the memory device.

10. The method of claim 1 , wherein the parallel plane structure in the programming mode comprises a first number of physical parallel planes;

wherein the parallel plane structure in the normal mode comprises a second number of physical parallel planes; and

wherein the first number of physical parallel planes is greater than the second number of physical parallel planes.

11. A host system for loading data from the host system into a memory device, the host system comprising:

a memory; and

a controller in communication with the memory, the controller configured to:

access a programming indicator, the programming indicator indicative of a parallel plane structure of multiple planes in different dies for writing the data to the memory device in a programming mode, wherein the memory device includes a different parallel plane structure for writing the data to the memory device in a normal mode;

identify a sequential stream of data for transmission to the memory device, wherein the sequential stream comprises a finite series of sections of data in sequential order;

use the programming indicator and the identified sequential stream of data in order to obtain interleaved data, the interleaved data comprising a reordering of the sequential stream of data conforming to the parallel plane structure of the multiple planes in the different dies such that the interleaved data comprises sequential data, according to the sequential order of the sequential stream of data, across the multiple planes within the dies and non-sequential data, according to the sequential order of the sequential stream of data, for the multiple planes across the different dies in order for the memory device to write the interleaved data in parallel in the programming mode; and

send the interleaved data sequentially to the memory device such that the memory device stores the sequential data, according to the sequential order of the sequential stream of data, across the multiple planes within the dies and the non-sequential data, according to the sequential order of the sequential stream of data, for the multiple planes across the different dies.

12. The host system of claim 11 , wherein the controller is configured to use the programming indicator and the identified sequential stream of data in order to obtain interleaved data by accessing the memory using the programming indicator and the identified sequential stream of data in order to obtain the interleaved data.

13. The host system of claim 11 , wherein the controller is configured to use the programming indicator and the identified sequential stream of data in order to obtain interleaved data by accessing the sequential stream of data and reordering the sequential stream of data using the programming indicator in order to generate the interleaved data.

14. The host system of claim 11 , wherein the programming indicator comprises a type of the memory device; and

wherein the controller is further configured to use a data construct to correlate the type of the memory device to a particular parallel plane structure.

15. The host system of claim 11 , wherein the controller is further configured to send a communication to the memory device, the communication indicative of the programming mode to the memory device in order for the memory device to configure itself to program the interleaved data in multiple pages across the different dies in parallel according to the programming mode.

16. The host system of claim 15 , wherein the sequential stream of data comprises a sequential stream of pages;

wherein the multiple dies comprise a first die and a second die; and

wherein the sequential stream of pages is reordered into the interleaved data such that after the memory device programs the interleaved data in multiple pages across the different dies according to the programming mode, the first die and the second die including stored pages in a sequence identical to the sequential stream of pages.

17. The host system of claim 15 , wherein the controller is further configured to send a second communication to the memory device, the second communication indicative of the normal mode to the memory device in order for the memory device to configure itself to program in a metablock size, the metablock size being smaller than a size of the multiple pages across the different dies in the programming mode.

18. The host system of claim 17 , wherein the metablock size consists of pages in a single die.

19. The host system of claim 11 , wherein the controller is configured to access the programming indicator is in response to a query to the memory device for the parallel plane structure of the memory device.

20. The host system of claim 11 , wherein the parallel plane structure in the programming mode comprises a first number of physical parallel planes;

wherein the parallel plane structure in the normal mode comprises a second number of physical parallel planes; and

wherein the first number of physical parallel planes is greater than the second number of physical parallel planes.