Low-cost non-volatile flash-RAM memory
A method of flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.
1. A method of manufacturing a flash-RAM comprising:
a. forming CMOS circuitry;
b. depositing a first metal layer upon the CMOS circuitry;
c. depositing a first magnetic tunnel junction (MTJ) layer on top of the metal layer to form a non-volatile random-access-memory (RAM);
d. depositing silicon oxide and silicon nitride on top of the non-volatile RAM;
e. performing chemical mechanical polishing (CMP) on the deposited silicon oxide and silicon nitride thereby leaving a smooth surface of silicon oxide and silicon nitride;
f. depositing a metal layer on top of the smooth surface;
g. depositing a diode layer on top of the metal layer;
h. depositing a second MTJ layer on top of the diode layer.
2. The method of manufacturing a flash-RAM as recited in claim 1 , further including etching the MTJ and the diode layer.
3. The method of manufacturing a flash-RAM as recited in claim 1 , wherein depositing another layer of silicon oxide and silicon nitride and repeating the steps e. through h. of claim 1 to form stacks of MTJ and further depositing another layer of silicon oxide and silicon nitride and performing CMP thereof.
4. The method of manufacturing a flash-RAM as recited in claim 1 , further depositing a magnetic shielding layer on top of the first MTJ layer prior to performing CMP in step e.
5. The method of manufacturing a flash-RAM as recited in claim 4 , further depositing a silicon dioxide layer on top of the magnetic shielding layer.
6. The method of manufacturing a flash-RAM as recited in claim 1 , further depositing additional magnetic shielding layer after performing CMPS.
7. The method of manufacturing a flash-RAM as recited in claim 1 , where the diode is formed by depositing a first layer made of Pt, Al, or Ti, a second layer formed on top of the first layer and made of Si, and a third layer formed on top of the second layer and made of N-doped Si.
8. The method of manufacturing a flash-RAM as recited in claim 7 , wherein the diode is substantially single crystalline.
9. The method of manufacturing a flash-RAM as recited in claim 8 , wherein seed layers are deposited to form the diode.
10. The method of manufacturing a flash-RAM as recited in claim 7 , wherein the diode is formed using flash annealing.
11. The method of manufacturing a flash-RAM as recited in claim 7 , wherein the diode is formed using laser annealing.
12. The method of manufacturing a flash-RAM as recited in claim 1 , where the diode is formed by depositing a first layer made of Pt, Al, or Ti, a second layer formed on top of the first layer and made of Si, and a third layer formed on top of the second layer and made of P-doped Si.
13. The method of manufacturing a flash-RAM as recited in claim 1 , further forming stacks with each stack having at least one MTJ and one diode, and further forming a metal stub and a transistor on top of a top stack connecting the MTJ to the transistor.