Memory device including transistor array with shared plate channel and method for making the same
View Patent ↗The present invention relates to memory devices incorporating therein a novel memory cell architecture which includes an array of selection transistors sharing a common channel and method for making the same. A memory device comprises a semiconductor substrate having a first type conductivity, a plurality of drain regions and a common source region separated by a common plate channel in the substrate, and a selection gate disposed on top of the plate channel with a gate dielectric layer interposed therebetween. The plurality of drain regions and the common source region have a second type conductivity opposite to the first type provided in the substrate.
1. A memory device comprising:
a semiconductor substrate having a first type conductivity;
a continuous common plate channel in the substrate that is shared by a plurality of drain regions disposed along a channel width direction;
the plurality of drain regions disposed along the channel width direction adjacent to a first side of the common plate channel;
a common source region that extends along the channel width direction and is disposed adjacent to a second side, opposite to the first side, of the common plate channel; and
a selection gate disposed above said continuous common plate channel with a gate dielectric layer interposed therebetween,
and wherein said plurality of drain regions and said common source region have a second type conductivity opposite to said first type provided in said substrate.
2. The memory device according to claim 1 , wherein said semiconductor substrate comprises silicon.
3. The memory device according to claim 1 , wherein said first type and second type conductivities are p type and n type, respectively.
4. The memory device according to claim 1 , wherein said gate dielectric layer comprises silicon oxide.
5. The memory device according to claim 1 , wherein said gate dielectric layer is formed of a compound comprising hafnium and oxygen.
6. The memory device according to claim 1 , wherein said selection gate comprises doped polysilicon.
7. The memory device according to claim 1 , wherein said selection gate comprises at least one layer formed of titanium nitride.
8. The memory device according to claim 1 wherein the plurality of drain regions are formed in the semiconductor substrate and each drain region is separated from an adjacent drain region by semiconductor substrate material having the first type conductivity.
9. A memory device comprising:
a semiconductor substrate having a first type conductivity;
a common source region in said substrate extending along a first direction;
a first common plate channel in said substrate having the first type conductivity and extending continuously along the first direction adjacent to a first side of the common source region;
a first plurality of drain regions in said substrate disposed adjacent to the first common plate channel, wherein the first common plate channel is shared by each of the first plurality of drain regions;
a first selection gate disposed above the first common plate channel with a first gate dielectric layer interposed therebetween;
a second common plate channel in said substrate having the first type conductivity and extending continuously along the first direction adjacent to a second side of the common source region opposite to the first side;
a second plurality of drain regions in said substrate disposed adjacent to the second common plate channel, wherein the second common plate channel is shared by each of the second plurality of drain regions; and
a second selection gate disposed above the second common plate channel with a second gate dielectric layer interposed therebetween,
wherein said first and second plurality of drain regions and said common source region have a second type conductivity opposite to the first type provided in the substrate.
10. The memory device according to claim 9 , wherein said semiconductor substrate comprises silicon.
11. The memory device according to claim 9 , wherein said first type and second type conductivities are p type and n type, respectively.
12. The memory device according to claim 9 , wherein said gate dielectric layer comprises silicon oxide.
13. The memory device according to claim 9 , wherein said gate dielectric layer is formed of a compound comprising hafnium and oxygen.
14. The memory device according to claim 9 , wherein said selection gate comprises doped polysilicon.
15. The memory device according to claim 9 further comprising:
a plurality of contacts, each of which is disposed on top of one of said first and second plurality of drain regions;
a plurality of resistive memory elements, each of which is disposed on top of one of said plurality of contacts; and
a plurality of parallel bit lines, each of which connects a series of resistive memory elements along a direction perpendicular to the first direction.
16. The memory device according to claim 15 , wherein said resistive memory elements comprise a precipitate bridging metal oxide consisting of NiO, TiO 2 , Sr(Zr)TiO 3 , or combinations thereof.
17. The memory device according to claim 15 , wherein said resistive memory elements comprise a phase change chalcogenide compound consisting of Ge 2 Sb 2 Te 5 or AgInSbTe.
18. The resistive memory device according to claim 15 , wherein said resistive memory elements comprise at least two layers of ferromagnetic materials with a layer of non-magnetic spacer interposed therebetween.
19. The memory device according to claim 15 , wherein said contacts are made of a conducting material comprising tungsten.
20. The memory device according to claim 9 wherein the first and second plurality of drain regions are formed in the semiconductor substrate and each drain region is separated from an adjacent drain region by semiconductor substrate material having the first type conductivity.
21. A method for fabricating a memory device comprising the steps of:
providing a semiconductor substrate having a first type conductivity;
forming a plurality of parallel selection gates on said substrate with a gate dielectric layer interposed therebetween;
forming a plurality of common source regions in said substrate by a first ion implantation process, the common source regions being disposed between adjacent parallel selection gates; and
forming a plurality of drain regions in said substrate by a second ion implantation process using a mask including parallel lines oriented perpendicular to the plurality of parallel selection gates,
wherein said plurality of common source regions and said plurality of drain regions have a second type conductivity opposite to said first type, and each of said plurality of common source regions is shared by at least two of said plurality of drain regions and by at least two common plate channels formed in said substrate beneath one of said plurality of parallel selection gates.
22. The method according to claim 21 , wherein said first type and second type conductivities are p type and n type, respectively.