IP Library › Granted Patent US 8,736,307
Granted Patent B2
US 8,736,307 · App. 13/360,927 · Granted May 27, 2014

Bidirectional transceiver and method

Inventors: Aurelio Pimentel (Shanghai, CN); James Lepkowski (Glendale, AZ); Frank Dover (Mesa, AZ); Senpeng Sheng (Chandler, AZ)
Assignee: Semiconductor Components Industries, LLC
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Quick Facts
Patent No.
US 8,736,307
App. No.
13/360,927
Granted
May 27, 2014
Kind
B2
Abstract

In accordance with an embodiment, a transceiver includes a bidirectional data transmission circuit coupled to a direction control circuit and method for transmitting electrical signals in one or more directions. The direction control circuit generates a comparison signal in response to comparing input/output signals of the bidirectional data transmission circuit. Transmission path enable signals are generated in response to the comparison signal.

Claims (38)

1. An autosensing bidirectional transceiver, comprising:

a bidirectional data transmission circuit having first and second input/output terminals, first and second input terminals, and first and second transmission paths, wherein the first signal transmission path comprises a first driver stage having an input terminal, an output terminal, and an enable terminal;

a comparator having first and second input terminals and an output terminal, the first input terminal of the comparator coupled to the first input/output terminal of the bidirectional data transmission circuit and the second input terminal of the comparator coupled to the second input/output terminal of the bidirectional data transmission circuit; and

a direction flag having an input terminal and a first output terminal, the input terminal of the direction flag coupled to the output terminal of the comparator

wherein the first driver stage comprises:

a first inverter having an input terminal and an output terminal; and

a second inverter having an input terminal, an output terminal, and an enable terminal, the input terminal of the second inverter coupled to the output of the first inverter.

2. The autosensing bidirectional transceiver of claim 1 , wherein

the first input terminal of the comparator is directly coupled to the first input/output terminal of the bidirectional data transmission circuit and the second input terminal of the comparator is directly coupled to the second input/output terminal of the bidirectional data transmission circuit.

3. The autosensing bidirectional transceiver of claim 2 , further including a delay element coupled between the output terminal of the comparator and the input of the direction flag.

4. The autosensing bidirectional transceiver of claim 3 , wherein the comparator is an exclusive OR logic gate.

5. The autosensing bidirectional transceiver of claim 3 , wherein the comparator is one of an analog comparator or a digital comparator.

6. The autosensing bidirectional transceiver of claim 3 , wherein the direction flag is a means for toggling between first and second logic states in response to a pulse at its input terminal.

7. The autosensing bidirectional transceiver of claim 3 , wherein the direction flag is a flip-flop.

8. The autosensing bidirectional transceiver of claim 3 , wherein a delay time of the delay element is longer than a total propagation delay of the comparator and the signal transmission path.

9. The autosensing bidirectional transceiver of claim 2 , further including a first direction control element coupled to the first signal transmission path and a second direction control element coupled to the second signal transmission path.

10. The autosensing bidirectional transceiver of claim 2 , wherein the first signal transmission path comprises a first driver stage having an input terminal, an output terminal, and an enable terminal.

11. The autosensing bidirectional transceiver of claim 1 , further including a first AND gate having first and second input terminals and an output terminal, the first input terminal coupled to the first output terminal of the direction flag and the output terminal coupled to the enable terminals of the first and second inverters.

12. The autosensing bidirectional transceiver of claim 11 , wherein the second signal transmission path comprises a second driver stage having an input terminal, an output terminal, and an enable terminal.

13. The autosensing bidirectional transceiver of claim 12 , wherein the second driver stage comprises:

a third inverter having an input terminal, an output terminal, and an enable terminal; and

a fourth inverter having an input terminal, an output terminal, and an enable terminal, the input terminal of the fourth inverter coupled to the output of the third inverter.

14. The autosensing bidirectional transceiver of claim 13 , wherein the direction flag has a second output terminal and further including a second AND gate having first and second input terminals and an output terminal, the first input terminal coupled to the second output terminal of the direction flag and the output terminal coupled to the enable terminals of the third and fourth inverters.

15. The autosensing bidirectional transceiver of claim 14 , wherein the output terminal of the fourth inverter is coupled to the input terminal of the first inverter and the output terminal of the second inverter is coupled to the input terminal of the third inverter.

16. The autosensing bidirectional transceiver of claim 15 , further including a first resistor coupled between the output terminal of the fourth inverter and the input terminal of the first inverter.

17. A method for transmitting electrical signals in a plurality of directions, comprising:

providing a bidirectional data transmission circuit having first and second input/output terminals, first and second input terminals, first and second signal transmission paths, a first signal transmission path between the first input/output terminal and the second input/output terminal configured to transmit an electrical signal from the first input/output terminal to the second input/output terminal through a first driver stage that includes an enable terminal and first and second inverters, wherein an input terminal of the second inverter is coupled to an output terminal of the first inverter, and a second signal transmission path between the second input/output terminal and the first input/output terminal configured to transmit another electrical signal between the second input/output terminal and the first input/output terminal;

generating a first comparison signal in response to comparing a first signal at the first input/output terminal with a second signal at the second input/output terminal;

generating a first enable signal in response to the first comparison signal being at a first logic voltage level; and

activating the first signal transmission path in response to the first enable signal at the enable terminal of the first driver stage.

18. The method of claim 17 , wherein generating the first enable signal comprises:

transmitting the first comparison signal through a delay element to an input terminal of a direction flag;

generating an output signal at an output terminal of the direction flag, the first output signal of the direction flag serving as the first input/output signal.

19. The method of claim 18 , wherein a delay through the delay element is longer than a propagation delay in generating the first comparison signal.

20. The method of claim 18 , further including:

generating a second comparison signal in response to comparing a third signal at the first input/output terminal with a fourth signal at the second input/output terminal;

generating a second enable signal in response to the second comparison signal being at a second logic voltage level; and

activating the second signal transmission path in response to the second enable signal.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2012
From: PIMENTEL, AURELIO; LEPKOWSKI, JAMES; DOVER, FRANK; SHENG, SENPENG
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 027615/0446 →
Continuity (1)
Related Publication 20130195153A1 · Aug 1, 2013