Method of packaging semiconductor die with cap element
View Patent ↗A method of assembling semiconductor devices includes placing an array of semiconductor dies on a die support. A cap array structure is provided that has a corresponding array of caps supported by a cap frame structure. The cap array structure and the array of semiconductor dies on the die support are aligned, with the caps extending over corresponding semiconductor dies, in a mold chase. The array of semiconductor dies and the array of caps are encapsulated with a molding compound in the mold chase. The encapsulated units of the semiconductor dies with the corresponding caps are removed from the mold chase and singulated. Singulating the encapsulated units may include removing the cap frame structure from the encapsulated units.
1. A method of assembling semiconductor devices, comprising:
placing an array of semiconductor dies on a die support, wherein said die support comprises a first set of alignment holes;
providing a cap array structure including a corresponding array of cap elements supported by a cap frame structure, wherein said cap array structure comprises a second set of alignment holes;
aligning said cap array structure and said array of semiconductor dies on said die support, wherein said cap elements extend over corresponding semiconductor dies, in a mold chase, wherein said mold chase includes location pins for positioning and aligning said cap array structure and said array of semiconductor dies on said die support using said first and second sets of alignment holes;
encapsulating said array of semiconductor dies and said array of cap elements with a molding compound; and
singulating encapsulated units of said semiconductor dies and cap elements.
2. The method of claim 1 , further comprising providing respective sets of external electrical contact surfaces connected to said semiconductor dies.
3. The method of claim 2 , wherein said die support comprises a temporary substrate that is removed after encapsulating said array of semiconductor dies and said array of cap elements, and wherein providing respective sets of external electrical contact surfaces includes applying electrical contact surfaces to said encapsulated units after removing said temporary substrate.
4. The method of claim 2 , wherein said die support comprises an electrically insulating substrate bearing said electrical contact surfaces.
5. The method of claim 2 , wherein said respective sets of external electrical contact surfaces include respective ball grid arrays.
6. The method of claim 2 , wherein said die support comprises a lead frame structure, and said lead frame structure includes said sets of external electrical contact surfaces and a supporting frame structure.
7. The method of claim 6 , wherein singulating said encapsulated units includes removing said supporting frame structure from said encapsulated units.
8. The method of claim 6 , wherein said lead frame structure includes an array of flags for receiving said array of semiconductor dies and supported initially by said supporting frame structure, wherein said sets of external electrical contact surfaces are disposed peripherally to said flags.
9. The method of claim 2 , wherein said sets of external electrical contact surfaces are connected to said semiconductor dies by wires bonded to said external electrical contact surfaces and to said dies before positioning said cap array structure and said array of semiconductor dies in said mold chase.
10. The method of claim 1 , wherein singulating said encapsulated units includes removing said cap frame structure from the encapsulated units.
11. The method of claim 1 , wherein said cap array structure comprises thermally conductive material so that said cap elements act as heat sinks for said semiconductor dies.
12. The method of claim 1 , wherein said cap array structure comprises electrically conductive material so that said cap elements provide electromagnetic shielding for said semiconductor dies.
13. The method of claim 1 , wherein said semiconductor dies comprise magneto-resistive random access memories and said cap array structure comprises high permeability magnetic material so that said cap elements provide magnetic shielding for said semiconductor dies.
14. The method of claim 1 , wherein said cap frame structure comprises cap frame members that form rectangular frames surrounding said cap elements respectively, the frame members being common to adjacent cap elements.
15. The method of claim 14 , wherein said cap elements are connected mechanically with said rectangular frames by ties at each corner of the rectangular frames, so that said rectangular frames and said ties at least temporarily support said cap elements.
16. The method of claim 15 , wherein said ties are inclined to a plane in which said rectangular frames extend, such that said cap elements are offset from said plane and are spaced from said semiconductor dies when said cap array structure is assembled with said array of semiconductor dies with said rectangular frames abutting said die support.