Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces
A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A duplex plated bump on lead pad is formed over the substrate. An insulating layer is formed over the first conductive layer and the substrate. A portion of the insulating over the duplex plated bump on lead pad is removed using a laser direct ablation process. The insulating layer is a lamination layer. The duplex plated bump on lead pad has a wide bump on lead pad. A semiconductor die is mounted over the substrate. The semiconductor die has a composite conductive interconnect structure. The semiconductor die has a first bump and a second bump with a pitch ranging from 90-150 micrometers between the first bump and the second bump. A duplex plated contact pad is formed on a surface of the substrate opposite the duplex plated bump-on-lead pad.
1 . A method of making a semiconductor device, comprising:
providing a substrate;
forming a first conductive layer over the substrate;
forming a duplex plated bump-on-lead (BOL) pad over the substrate to include a first portion of the first conductive layer, the duplex plated BOL pad being vertically offset and electrically isolated from a second portion of the first conductive layer; and
forming an insulating layer over the first conductive layer and the substrate.
2 . The method of claim 1 , wherein the insulating layer includes a lamination layer.
3 . The method of claim 1 , further including forming a duplex plated contact pad over a surface of the substrate opposite the duplex plated BOL pad.
4 . The method of claim 1 , further including disposing a semiconductor die over the substrate.
5 . The method of claim 4 , further including forming a composite conductive interconnect structure over the semiconductor die.
6 . The method of claim 1 , further including forming a second conductive layer over the first conductive layer.
7 . A method of making a semiconductor device, comprising:
providing a substrate;
forming a plurality of conductive segments over the substrate;
forming a duplex plated bump-on-lead (BOL) pad over the substrate and vertically offset from adjacent ones of the conductive segments; and
forming an insulating layer over the substrate and the duplex plated BOL pad.
8 . (canceled)
9 . The method of claim 7 , further including removing a portion of the insulating layer over the duplex plated BOL pad by a laser direct ablation (LDA) process.
10 . The method of claim 7 , further including forming a duplex plated contact pad over a surface of the substrate opposite the duplex plated BOL pad.
11 . The method of claim 7 , further including disposing a semiconductor die over the substrate.
12 . The method of claim 11 , further including forming a first bump and a second bump over the semiconductor die with a pitch ranging from 90-150 micrometers (μm) between the first bump and the second bump.
13 . The method of claim 7 , wherein forming the plurality of conductive segments includes:
forming a first conductive layer over the substrate; and
forming a second conductive layer over the first conductive layer.
14 . A method of making a semiconductor device, comprising:
providing a substrate; and
forming a duplex plated bump-on-lead (BOL) pad over the substrate.
15 . The method of claim 14 , further including forming a conductive layer over the substrate.
16 . The method of claim 14 , further including forming an insulating layer over the substrate.
17 . The method of claim 14 , wherein the duplex plated BOL pad includes a wide BOL pad.
18 . The method of claim 14 , further including forming a duplex plated contact pad on a surface of the substrate opposite the duplex plated BOL pad.
19 . The method of claim 14 , further including disposing a semiconductor die over the substrate.
20 . A semiconductor device, comprising:
a substrate; and
a duplex plated bump-on-lead (BOL) pad formed over the substrate.
21 . The semiconductor device of claim 23 , wherein a surface of the duplex plated BOL pad is exposed from the insulating layer.
22 . The semiconductor device of claim 20 , further including a conductive layer formed over the substrate.
23 . The semiconductor device of claim 20 , further including an insulating layer formed over the substrate and duplex plated BOL pad.
24 . The semiconductor device of claim 20 , wherein the duplex plated BOL pad includes a wide BOL pad.
25 . The semiconductor device of claim 20 , further including a semiconductor die disposed over the substrate.
26 . The semiconductor device of claim 20 , further including a conductive layer formed over the substrate, wherein the duplex plated BOL pad is vertically offset from the conductive layer.
27 . The semiconductor device of claim 23 , wherein the insulating layer includes a lamination layer.
28 . The semiconductor device of claim 20 , further including a plurality of conductive segments formed over the substrate, wherein the duplex plated BOL pad is vertically offset from adjacent ones of the conductive segments.
29 . The method device of claim 14 , further including:
forming a conductive layer over the substrate; and
forming the duplex plated BOL pad vertically offset from the conductive layer.
30 . The method of claim 16 , wherein the insulating layer includes a lamination layer.
31 . The method of claim 14 , further including:
forming a plurality of conductive segments over the substrate; and
forming the duplex plated BOL pad vertically offset from adjacent ones of the conductive segments.