IP Library › Granted Patent US 9,077,367
Granted Patent B2
US 9,077,367 · App. 13/428,905 · Granted Jul 7, 2015

Bit length converting circuit for floating-point numbers, and vibration correction control circuit using the bit length converting circuit

Inventor: Hideki Hirayama (Gifu, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H03M7/24H04N5/23258
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Quick Facts
Patent No.
US 9,077,367
App. No.
13/428,905
Granted
Jul 7, 2015
Kind
B2
Abstract

The bit length reducing unit reduces the bit length of an operand expressed by a floating-point number and outputs the operand to a computing unit. The bit length increasing unit increases the bit length of the result value of operation represented by the floating-point number inputted from the computing unit and restores the original bit length. The bit length reducing unit discards a preset number of higher-order bits of the exponent part of the floating-point number and at the same time adds a positive or negative offset value to the exponent part with the higher-order bits discarded, according to an application to be executed by the computing unit. The bit length increasing unit restores the bits discarded by the bit length reducing unit 11 from the exponent part of the floating-point number and at the same time subtracts an offset value from the exponent part.

Claims (24)

1. A vibration correction control circuit for correcting an optical axis of an image pickup apparatus in response to a vibration thereof, the circuit comprising:

a vibration-component signal generating unit configured to generate a vibration-component signal indicating an amount of movement of an image pickup apparatus according to an output signal of a vibration detecting element for detecting a vibration of the image pickup apparatus;

a driver signal generating unit configured to generate a drive signal used to control a driver element to correct a position of a lens, based on an output signal of a position detecting element for detecting the position of the lens to be driven and the vibration-component signal; and

a bit length converting circuit for a floating-point number configured to convert the bit length of the output signal of the vibration detecting element expressed by the floating-point number, the bit length converting circuit comprising:

a bit length reducing unit configured to reduce a bit length of an operand expressed by the floating-point number and configured to output the operand to a computing unit; and

a bit length increasing unit configured to increase the bit length of a result value of operation represented by the floating-point number inputted from the computing unit and configured to restore an original bit length, wherein said bit length reducing unit discards a predetermined number of higher-order bits of the exponent part of the floating-point number and adds a positive or negative offset value to the exponent part with the higher-order bits discarded, according to an application to be executed by the computing unit, and wherein said bit length increasing unit restores a bit discarded by the bit length reducing unit from the exponent part of the floating-point number and subtracts the offset value from the exponent part thereof, and wherein said vibration-component signal generating unit includes: a high-pass filter configured to filter the output signal of the vibration detecting element, whose bit length has been converted by said bit length converting circuit, with a preset cutoff frequency; and an integration circuit configured to generate the vibration-component signal by integrating an output signal of the high-pass filter, wherein the high-pass filter and the integrating circuit comprises digital filters.

2. A bit length converting circuit for floating-point numbers according to claim 1 , wherein said bit length reducing unit discards a predetermined number of lower-order bits of the fraction part of the floating-point number by performing a rounding processing on the predetermined number of lower order bits thereof, and wherein said bit length increasing unit places zeros in bit positions, of the fraction part of the floating-point number, which is discarded by said bit length reducing unit and restores the bit length of the fraction part thereof to the original bit length.

3. A vibration correction control circuit according to claim 1 , wherein said bit length reducing unit discards a predetermined number of higher-order bits of the exponent part of the floating-point number and adds a negative offset value to the exponent part with the higher-order bits discarded, according to an arithmetic operation processing executed by the high-pass filter and the integration circuit.

4. The bit length converting circuit of claim 1 , wherein the bit length increasing unit comprises:

a comparing unit;

a subtracting unit coupled to the comparing unit; and

a bit adding unit coupled to the comparing unit and the subtracting unit.

5. A vibration correction control circuit for correcting an optical axis of an image pickup apparatus in response to a vibration thereof, the circuit comprising:

a vibration-component signal generating unit configured to generate a vibration-component signal indicating an amount of movement of an image pickup apparatus according to an output signal of a vibration detecting element for detecting a vibration of the image pickup apparatus;

a driver signal generating unit configured to generate a drive signal used to control a driver element to correct a position of image pickup devices, based on an output signal of a position detecting element for detecting the position of the image pickup devices to be driven and the vibration-component signal; and

a bit length converting circuit for floating-point numbers configured to convert the bit length of the output signal of the vibration detecting element expressed by the floating-point numbers, the bit length converting circuit comprising:

a bit length reducing unit configured to reduce a bit length of an operand expressed by a floating-point number of the floating point numbers and configured to output the operand to a computing unit; and

a bit length increasing unit configured to increase the bit length of a result value of operation represented by the floating-point number inputted from the computing unit and configured to restore an original bit length, wherein said bit length reducing unit discards a predetermined number of higher-order bits of the exponent part of the floating-point number and adds a positive or negative offset value to the exponent part with the higher-order bits discarded, according to an application to be executed by the computing unit, and wherein said bit length increasing unit restores a bit discarded by the bit length reducing unit from the exponent part of the floating-point number and subtracts the offset value from the exponent part thereof, and wherein, said vibration-component signal generating unit including: a high-pass filter configured to filter the output signal of the vibration detecting element, whose bit length has been converted by said bit length converting circuit, with a preset cutoff frequency; and an integration circuit configured to generate the vibration-component signal by integrating an output signal of the high-pass filter, wherein the high-pass filter and the integrating circuit comprises digital filters.

6. A vibration correction control circuit according to claim 5 , wherein said bit length reducing unit discards a predetermined number of higher-order bits of the exponent part of the floating-point number and adds a negative offset value to the exponent part with the higher-order bits discarded, according to an arithmetic operation processing executed by the high-pass filter and the integration circuit.

7. The bit length converting circuit of claim 5 , wherein the bit length increasing unit comprises:

a comparing unit;

a subtracting unit coupled to the comparing unit; and

a bit adding unit coupled to the comparing unit and the subtracting unit.

8. A bit length converting circuit for floating-point numbers according to claim 5 , wherein said bit length reducing unit discards a predetermined number of lower-order bits of the fraction part of the floating-point number by performing a rounding processing on the predetermined number of lower order bits thereof, and wherein said bit length increasing unit places zeros in bit positions, of the fraction part of the floating-point number, which is discarded by said bit length reducing unit and restores the bit length of the fraction part thereof to the original bit length.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2012
From: HIRAYAMA, HIDEKI
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 027920/0226 →
Priority Claims (1)
JP 2011-066489 · Mar 24, 2011 · national
Continuity (1)
Related Publication 20120242848A1 · Sep 27, 2012