Granted Patent B1

US 8,385,108 · App. 13/429,293 · Granted Feb 26, 2013

Abstract

Claims (34)

1. A magnetic memory array comprising:

a magnetic memory cell including a pair of magnetic tunnel junctions (MTJs);

an access transistor coupled between a first MTJ of the pair of MTJs and a second MTJ of the pair of MTJs;

a word line coupled to the access transistor;

magnetic memory cells arranged in a column alternately coupled to a first and second pair of bit lines, each bit line of the pair coupled to a MTJ of the pair of MTJs;

a read access transistor coupling adjacent magnetic memory cells;

a read word line coupled to the read access transistor;

a first and a second pair of current sources, each current sources of the pair coupled to a bit line (BL) of the first and second pair of bit lines respectively;

a first and a second sense amplifier coupled to the first and second pair of bit lines respectively;

the magnetic memory array operable to,

select the magnetic memory cell; and

set a bit line (BL) coupled to the magnetic memory cell to a voltage level, indicative of a certain state, that causes current to flow through the pair of MTJs in a manner that causes the direction of current flow through one of the MTJs of the pair of MTJs to be in a direction opposite to that of the other MTJ of the pair of MTJs to write to the magnetic memory cell.

2. The magnetic memory array, as recited in claim 1 , wherein selecting is performed by setting the word line (WL), to a voltage level, indicative of a particular state, that causes the selection of the magnetic memory cell through the transistor and setting all remaining word lines to a voltage level indicative of a state that is opposite to the particular state.

3. The magnetic memory array, as recited in claim 1 , wherein further setting all remaining word lines to a voltage level indicative of a state that is opposite to the certain state.

4. A magnetic memory array comprising:

a magnetic memory cell including a pair of magnetic tunnel junctions (MTJs);

a transistor coupled between a first MTJ of the pair of MTJs and a second MTJ of the pair of MTJs;

a word line coupled to the access transistor;

magnetic memory cells in a column alternatively coupled to a first and second pair of bit lines, each bit line of the pair coupled to a MTJ of the pair of MTJs;

a read access transistor coupling adjacent magnetic memory cells;

a read word line coupled to the read access transistor;

a first and a second pair of current sources, each current sources of the pair coupled to a bit line (BL) of the first and second pair of bit lines respectively;

a first and a second sense amplifier coupled to the first and second pair of bit lines respectively;

the array operable to,

select a magnetic memory cell of a magnetic memory array to be read, the magnetic memory cell including a pair of MTJs;

program one of the MTJs of the pair of MTJs to be ‘high’;

program another of the MTJs of the pair of MTJs to be ‘low’;

compare the current through the one MTJ to the current through the another MTJ; and

based on the comparison, declare the state of the magnetic memory cell to read the magnetic memory cell.

5. The magnetic memory array, as recited in claim 4 , wherein the magnetic memory array further operable to turn ‘off’ the word line (WL).

6. The magnetic memory array, as recited in claim 5 , wherein the magnetic memory array further operable to turn ‘on’ the read word lines that are immediately adjacent to the WL.

7. The magnetic memory array, as recited in claim 6 , wherein the further the magnetic memory is operable to determine if the magnetic memory cell is even or odd.

8. The magnetic memory array, as recited in claim 7 , wherein the magnetic memory array further being operable to upon determining the magnetic memory cell is even, set first pair of bit lines to ‘high’, allow the second pair of bit lines to float, the second pair of current sources and the second sense amplifier, read the data stored in the magnetic memory cell.

9. The magnetic memory array, as recited in claim 8 , wherein the magnetic memory array being further operable to determine the magnetic memory cell is odd, set second pair of bit lines to ‘high’, allow the first pair of bit lines to float, activate the first pair of current sources the first sense amplifier, and reading the data stored in the magnetic memory cell.

Assignments (6)