Techniques for enabling multiple V
View Patent ↗Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.
1. A semiconductor device comprising:
a substrate having at least a first and a second nFET region, and at least a first and a second pFET region;
at least one logic nFET on the substrate over the first nFET region;
at least one logic pFET on the substrate over the first pFET region;
at least one SRAM nFET on the substrate over the second nFET region; and
at least one SRAM pFET on the substrate over the second pFET region,
wherein each of the logic nFET, logic pFET, SRAM nFET and SRAM pFET comprises a gate stack having a metal layer over a high-K layer,
wherein the logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, and wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET;
combination spacers adjacent to each of the gate stacks, wherein the combination spacers comprise nitride spacers adjacent to the gate stacks and oxide spacers adjacent to the nitride spacers; and
a dual stressed nitride liner over the device, wherein the oxide spacers separate the dual stressed nitride liner from the nitride spacers.
2. The device of claim 1 , wherein the first and second nFET regions and the first and second pFET regions comprise silicon.
3. The device of claim 1 , wherein the substrate comprises one or more of a silicon-on-insulator substrate and a bulk silicon substrate.
4. The device of claim 1 , wherein the SRAM pFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, the capping layer being configured to shift the threshold voltage of the SRAM pFET relative to the threshold voltage of one or more of the logic nFET, logic pFET and SRAM nFET.
5. The device of claim 1 , wherein the metal layer comprises one or more of titanium nitride, tantalum nitride, tantalum aluminum nitride, titanium aluminum nitride and tantalum carbide.
6. The device of claim 1 , wherein the capping layer comprises one or more of lanthanum oxide, magnesium oxide, oxides of group IIA and group IIIB elements and nitrides of group IIA and group IIIB elements.
7. The device of claim 1 , wherein the high-K layer comprises one or more of hafnium oxide, zirconium oxide, hafnium silicate, nitrided hafnium silicate, tantalum oxide, titanium oxide, aluminum oxide and mixtures comprising at least one of the foregoing high-K materials.
8. The device of claim 1 , wherein the logic nFET, logic pFET, SRAM nFET and SRAM pFET gate stacks each further comprise a silicon layer over the metal layer.
9. The device of claim 8 , wherein the silicon layer comprises one or more of polysilicon and amorphous silicon.
10. The device of claim 1 , wherein the logic nFET, logic pFET, SRAM nFET and SRAM pFET gate stacks each further comprise an interfacial layer dielectric separating the high-K layer from the substrate.
11. The device of claim 1 , wherein the substrate further comprises one or more shallow trench isolation regions present therein between at least two of the first nFET region, the second nFET region, the first pFET region and the second pFET region.
12. The device of claim 1 , wherein the logic pFET and SRAM pFET gate stack are oxidized so as to shift the threshold voltage of the logic pFET and SRAM pFET relative to a threshold voltage of one or more of the logic nFET and SRAM nFET.
13. The device of claim 1 , wherein the dual stressed liner comprises a tensile silicon nitride layer over the logic nFET and SRAM nFET, and a compressive silicon nitride layer over the logic pFET and SRAM pFET.
14. An integrated circuit comprising:
a substrate having at least a first and a second nFET region, and at least a first and a second pFET region;
at least one logic nFET on the substrate over the first nFET region;
at least one logic pFET on the substrate over the first pFET region;
at least one SRAM nFET on the substrate over the second nFET region; and
at least one SRAM pFET on the substrate over the second pFET region,
wherein each of the logic nFET, logic pFET, SRAM nFET and SRAM pFET comprises a gate stack having a metal layer over a high-K layer,
wherein the logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, and wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET;
combination spacers adjacent to each of the gate stacks, wherein the combination spacers comprise nitride spacers adjacent to the gate stacks and oxide spacers adjacent to the nitride spacers; and
a dual stressed nitride liner over the device, wherein the oxide spacers separate the dual stressed nitride liner from the nitride spacers.