CCD image sensors and methods

1. An image sensor comprising:

an array of photosensitive pixels arranged in columns;

a plurality of vertical CCDs each associated with one of the columns of pixels;

a plurality of sense nodes each associated with and accepting charge from the vertical CCDs and converting the charge into a voltage; and

one or more delay stages for outputting charges from two or more vertical CCDs into one of the sense nodes, the one or more delay stages being configured to combine charges from the two or more vertical CCDs prior to output to the one of the sense nodes;

readout circuitry for accepting voltage from the plurality of sense nodes and, based thereon, outputting signals for reconstruction into an image sensed by the array of photosensitive pixels.

2. The image sensor of claim 1 , wherein the readout circuitry comprises a discrete column readout circuit associated with each sense node.

3. The image sensor of claim 2 , wherein each column readout circuit comprises circuitry for subtracting a reference value from the sense nodes from a signal value from the sense nodes.

4. The image sensor of claim 1 , wherein the array of photosensitive pixels, the plurality of vertical CCDs, the plurality of sense nodes, and the readout circuitry are all portions of a single monolithic integrated circuit.

5. The image sensor of claim 1 , wherein the readout circuitry comprises a readout circuit shared by two or more vertical CCDs and the delay stages include delay registers disposed between the two or more vertical CCDs and the sense node associated therewith.

6. The image sensor of claim 1 , wherein the readout circuitry comprises (i) a first portion disposed on a first side of the array of photosensitive pixels and (ii) a second portion disposed on a second side of the array of photosensitive pixels different from the first side.

7. The image sensor of claim 6 , wherein the first side and the second side are opposite sides.

8. The image sensor of claim 6 , wherein some of the plurality of sense nodes are disposed on the first side and some others of the plurality of sense nodes are disposed on the second side.

9. The image sensor of claim 1 , wherein each sense node comprises a floating diffusion, a reset transistor, and an amplifier.

10. The image sensor of claim 1 , wherein the image sensor has an interline architecture in which each vertical CCD is proximate the column of pixels associated therewith.

11. The image sensor of claim 1 , wherein the image sensor has a full-frame architecture in which each vertical CCD is the column of pixels associated therewith.

12. The image sensor of claim 1 , wherein the one or more delay stages is configured to combine charges from alternating vertical CCDs.

13. A method of operating an image sensor comprising an array of photosensitive pixels arranged in columns, a vertical CCD associated with each column of pixels, a plurality of sense nodes each associated with two or more of the vertical CCDs, and one or more delay stages between the each vertical CCDs and the sense node, the method comprising:

outputting charge from each vertical CCD into the one or more delay stages associated therewith;

combining charge from a plurality of vertical CCDs in the one or more delay stages; and

converting the combined charge from delay stages into voltage with the associated sense node to form a plurality of different sense voltages;

reading out the plurality of sense voltages for reconstruction into an image sensed by the array of photosensitive pixels.

14. The method of claim 13 , wherein the charge conversion and reading out are performed for a first portion of the photosensitive pixels on a first side of the array and for a second portion of the photosensitive pixels on a second side of the array different from the first side.

15. The method of claim 13 , wherein combining charge from a plurality of vertical CCDs includes combining charges from alternating CCDs.