Method and system for planar regrowth in GAN electronic devices
View Patent ↗A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.
1. A vertical JFET comprising:
a III-nitride substrate;
a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate, wherein the first III-nitride epitaxial layer has a first dopant concentration;
a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer, wherein the III-nitride epitaxial structure comprises:
a set of channels of the first conductivity type and having a second dopant concentration, wherein each of the channels comprises an interface surface;
a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, wherein each of the sources comprises a contact surface containing an interface surface of the channels;
a set of regrown gates interleaved with the set of channels, wherein an upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.
2. The vertical JFET of claim 1 further comprising:
a set of source contacts, each being electrically coupled to the set of sources; and
a set of gate contacts, each being electrically coupled to the set of regrown gates.
3. The vertical JFET of claim 1 further comprising a drain contact electrically coupled to the III-nitride substrate.
4. The vertical JFET of claim 1 wherein the first conductivity type is n type and the set of regrown gates are p type.
5. The vertical JFET of claim 1 wherein at least one of the first dopant concentration, the second dopant concentration, or the third dopant concentration is non-uniform.
6. The vertical JFET of claim 1 wherein a thickness of the III-nitride epitaxial layer is between 1 μm and 100 μm.
7. The vertical JFET of claim 1 wherein the set of channels are disposed between gates of the set of regrown gates such that current flow during operation of the vertical JFET is along a direction orthogonal to the upper surface of the set of regrown gates.
8. The vertical JFET of claim 1 wherein the III-nitride substrate comprises an n-type substrate.
9. The vertical JFET of claim 1 wherein the III-nitride epitaxial layer comprises an n-type GaN epitaxial layer having a dopant concentration less than or equal to a dopant concentration of the III-nitride substrate and a thickness greater than 1 μm.
10. The vertical JFET of claim 1 wherein a width of the set of channels measured along a direction orthogonal to a thickness of the III-nitride epitaxial layer is less than 5 μm.
11. The vertical JFET of claim 1 wherein the set of gates comprise a p-type III-nitride material.
12. The vertical JFET of claim 1 wherein the set of gates are further electrically coupled to the drift region.