Method and system for a gallium nitride vertical JFET with self-aligned gate metallization
View Patent ↗A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.
1. A method for fabricating a vertical JFET, the method comprising:
providing a III-nitride substrate of a first conductivity type;
forming a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate;
forming a second III-nitride epitaxial layer of the first conductivity type coupled to the first III-nitride epitaxial layer;
removing at least a portion of the second III-nitride epitaxial layer to expose a sidewall of the second III-nitride epitaxial layer;
removing at least a portion of the first III-nitride epitaxial layer to form a channel region of the vertical JFET, wherein the channel region has a channel sidewall;
forming a III-nitride gate structure of a second conductivity type coupled to the channel sidewall, wherein a top of the III-nitride gate structure is lower than a top of the second III-nitride epitaxial layer; and
forming a gate metal electrically coupled to the III-nitride gate structure and laterally self-aligned with respect to the sidewall of the second III-nitride epitaxial layer, wherein forming the gate metal comprises:
forming a first masking layer covering the top of the second III-nitride epitaxial layer;
depositing a metal layer to form a first metal structure on the first masking layer;
forming a second metal structure on the top of the III-nitride gate structure, wherein the first metal structure and the second metal structure are vertically spaced apart by a source spacer; and
removing the first masking layer and the source spacer to lift off the first metal structure, preserving the second metal structure to form the laterally self-aligned gate metal.
2. The method of claim 1 wherein removing at least a portion of the second III-nitride epitaxial layer further comprises removing another portion of the first III-nitride epitaxial layer to form an extension region having an extension sidewall laterally displaced from the channel sidewall.
3. The method of claim 1 wherein the sidewall of the second III-nitride epitaxial layer is substantially vertical.
4. The method of claim 1 wherein the channel sidewall is laterally self-aligned with respect to the sidewall of the second III-nitride epitaxial layer.
5. The method of claim 1 wherein the first masking layer and the source spacer comprise a dielectric material and removing the first masking layer and the source spacer comprises performing a wet etching process.
6. The method of claim 1 wherein a lateral width of the gate metal is equal to a lateral width of the III-nitride gate structure.
7. The method of claim 1 wherein a lateral width of the gate metal is less than a lateral width of the III-nitride gate structure.
8. The method of claim 1 wherein the vertical sidewall of the channel region is spaced apart from and laterally self-aligned with respect to the vertical sidewall of the second III-nitride epitaxial layer by a source spacer.
9. The method of claim 8 wherein a top of the III-nitride gate structure is spaced apart from and vertically self-aligned with respect to a top of the second III-nitride epitaxial layer by the source spacer.
10. A method for fabricating a vertical JFET, the method comprising:
providing a III-nitride substrate of a first conductivity type;
forming a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate;
forming a second III-nitride epitaxial layer of the first conductivity type coupled to the first III-nitride epitaxial layer;
removing at least a portion of the second III-nitride epitaxial layer to expose a sidewall of the second III-nitride epitaxial layer;
removing at least a portion of the first III-nitride epitaxial layer to form a channel region of the vertical JFET, wherein the channel region has a channel sidewall;
forming a III-nitride gate structure of a second conductivity type coupled to the channel sidewall, wherein a top of the III-nitride gate structure is lower than a top of the second III-nitride epitaxial layer;
forming a gate metal structure coupled to the III-nitride gate structure, wherein the gate metal structure is self-aligned to the vertical sidewall of the channel region;
forming a dielectric layer that at least partially covers the gate metal structure and a top of the second III-nitride epitaxial layer;
at least partially planarizing the dielectric layer;
removing a portion of the dielectric layer to expose the top of the second III-nitride epitaxial layer; and
forming a pad metal structure coupled to the exposed surface of the second III-nitride epitaxial layer.
11. The method of claim 10 wherein the gate metal structure is laterally separated from the vertical sidewall of the channel region by a gate spacer.
12. The method of claim 1 further comprising separating the pad metal structure into a source electrode and a gate electrode, the source electrode being coupled to the exposed surface of the second III-nitride epitaxial layer and the gate electrode being coupled to the gate metal structure.
13. The method of claim 10 wherein removing at least a portion of the second III-nitride epitaxial layer further comprises removing another portion of the first III-nitride epitaxial layer to form an extension region having an extension sidewall laterally displaced from the channel sidewall.
14. The method of claim 10 wherein the sidewall of the second III-nitride epitaxial layer is substantially vertical.
15. The method of claim 10 wherein the channel sidewall is laterally self-aligned with respect to the sidewall of the second III-nitride epitaxial layer.
16. The method of claim 10 further comprising forming a gate metal electrically coupled to the III-nitride gate structure, wherein the gate metal is laterally self-aligned with respect to the sidewall of the second III-nitride epitaxial layer.
17. The method of claim 16 wherein forming the gate metal comprises:
forming a first masking layer covering the top of the second III-nitride epitaxial layer;
depositing a metal layer to form a first metal structure on the first masking layer;
forming a second metal structure on the top of the III-nitride gate structure, wherein the first metal structure and the second metal structure are vertically spaced apart by a source spacer; and
removing the first masking layer and the source spacer to lift off the first metal structure, preserving the second metal structure to form the laterally self-aligned gate metal.
18. The method of claim 17 wherein the first masking layer and the source spacer comprise a dielectric material and removing the first masking layer and the source spacer comprises performing a wet etching process.
19. The method of claim 16 wherein a lateral width of the gate metal is equal to a lateral width of the III-nitride gate structure.
20. The method of claim 16 wherein a lateral width of the gate metal is less than a lateral width of the III-nitride gate structure.
21. The method of claim 10 wherein the vertical sidewall of the channel region is spaced apart from and laterally self-aligned with respect to the vertical sidewall of the second III-nitride epitaxial layer by a source spacer.
22. The method of claim 21 wherein a top of the III-nitride gate structure is spaced apart from and vertically self-aligned with respect to a top of the second III-nitride epitaxial layer by the source spacer.
23. The method of claim 1 wherein depositing a metal layer to form a first metal structure on the first masking layer and forming a second metal structure on the top of the III-nitride gate structure are performed concurrently.
24. The method of claim 1 wherein the gate metal is laterally separated from the vertical sidewall of the channel region by a gate spacer.
25. The method of claim 10 wherein depositing a metal layer to form a first metal structure on the first masking layer and forming a second metal structure on the top of the III-nitride gate structure are performed concurrently.
26. The method of claim 10 further comprising separating the pad metal structure into a source electrode and a gate electrode, the source electrode being coupled to the exposed surface of the second III-nitride epitaxial layer and the gate electrode being coupled to the gate metal structure.