Method and system for a GAN vertical JFET with self-aligned source metallization
View Patent ↗A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.
1. A semiconductor device comprising:
a III-nitride substrate;
a channel structure coupled to the III-nitride substrate, wherein the channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls;
a source region coupled to the channel structure, wherein the source region comprises a second III-nitride epitaxial material;
a III-nitride gate structure coupled to the one or more channel sidewalls;
a gate metal structure in electrical contact with the III-nitride gate structure; and
a dielectric layer overlying at least a portion of the gate metal structure, wherein a top surface of the dielectric layer is substantially co-planar with a top surface of the source region.
2. The semiconductor device of claim 1 further comprising a pad metal structure coupled to the top surface of the dielectric layer and electrically coupled to the second III-nitride epitaxial material.
3. The semiconductor device of claim 2 wherein the source region is characterized by a peripheral dimension defining a top surface area and the pad metal structure is in electrical contact with the top surface area.
4. The semiconductor device of claim 1 wherein the channel structure comprises a first portion having a first lateral width and a second portion having a second lateral width less than the first lateral width.
5. The semiconductor device of claim 4 wherein the gate metal structure is laterally self-aligned with respect to the second portion.
6. The semiconductor device of claim 1 wherein:
the III-nitride substrate, the first III-nitride epitaxial material, and the second III-nitride epitaxial material are of a first conductivity type; and
the III-nitride gate structure is of a second conductivity type.
7. The semiconductor device of claim 1 wherein:
the semiconductor device comprises a vertical JFET; and
the III-nitride substrate comprises a drain of the vertical JFET.