IP Library Granted Patent US 8,742,262
Granted Patent B2
US 8,742,262 · App. 13/483,837 · Granted Jun 3, 2014

Low temperature co-fired ceramic structure for high frequency applications and process for making same

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Quick Facts
Patent No.
US 8,742,262
App. No.
13/483,837
Granted
Jun 3, 2014
Kind
B2
Abstract

Disclosed herein is a multilayer low temperature co-fired ceramic (LTCC) structure comprising a multilayer low temperature co-fired ceramic comprising glass-ceramic dielectric layers with screen printed thick film inner conductors on portions of the layers and with thin film outer conductors deposited on the upper and lower outer surfaces of the LTCC. At least a portion of the thin film outer conductors is patterned in the form of lines and the spacings between the lines are less then 50 μm. Also disclosed is a process for making the LTCC structure.

Claims (40)

1. A multilayer low temperature co-fired ceramic structure comprising:

a) a multilayer low temperature co-fired ceramic comprising glass-ceramic dielectric layers with screen printed thick film inner conductors on portions of said layers and with screen printed thick film via interconnects between said inner conductors and from said inner conductors to the upper and lower outer surfaces of said low temperature co-fired ceramic, wherein the upper and lower outer surfaces of said low temperature co-fired ceramic have been polished subsequent to firing; and

b) thin film outer conductors deposited on said polished upper and lower outer surfaces of said low temperature co-fired ceramic, wherein said thin film outer conductors are patterned such that at least a portion of said thin film outer conductors is in the form of lines and wherein the spacings between said lines are less then 50 μm;

said thick film inner conductors and said thick film via interconnects between said inner conductors, said thin film outer conductors, and said thick film via interconnects from said inner conductors to said upper and lower outer surfaces all comprising precious metals independently selected from a group consisting of gold, silver, platinum, palladium, mixtures thereof and alloys thereof and wherein said thick film via interconnects from said inner conductors to said upper and lower outer surfaces provide electrical connections to said thin film outer conductors.

2. The multilayer low temperature co-fired ceramic structure of claim 1 , wherein said spacings between said lines are less then 10 μm.

3. The multilayer low temperature co-fired ceramic structure of claim 2 , wherein said spacings between said lines are 1-2 μm.

4. The multilayer low temperature co-fired ceramic structure of claim 1 , wherein said thick film inner conductors and said thick film via interconnects between said inner conductors are silver, wherein said thin film outer conductors are gold, and wherein said thick film via interconnects from said inner conductors to said upper and lower surfaces are a mixture of silver and gold.

5. The multilayer low temperature co-fired ceramic structure of claim 1 , wherein said thick film inner conductors and said thick film via interconnects between said inner conductors are silver, wherein said thin film outer conductors are gold, and wherein said thick film via interconnects from said inner conductors to said upper and lower surfaces are 20-100 wt % gold and 0-80 wt % silver.

6. The multilayer low temperature co-fired ceramic structure of claim 1 , wherein said thick film inner conductors and said thick film via interconnects between said inner conductors, said thin film outer conductors, and said thick film via interconnects from said inner conductors to said upper and lower surfaces are all gold.

7. A multilayer low temperature co-fired ceramic structure comprising:

a) a multilayer low temperature co-fired ceramic comprising glass-ceramic dielectric layers with screen printed thick film inner conductors on portions of said layers and with screen printed thick film via interconnects between said inner conductors and from said inner conductors to one outer surface of said low temperature co-fired ceramic, wherein said one outer surface of said low temperature co-fired ceramic has been polished subsequent to firing; and

b) a thin film outer conductor deposited on said polished one outer surface of said low temperature co-fired ceramic, wherein said thin film outer conductor is patterned such that at least a portion of said thin film outer conductor is in the form of lines and wherein the spacings between said lines are less then 50 μm;

said thick film inner conductors and said thick film via interconnects between said inner conductors, said thin film outer conductor, and said thick film via interconnects from said inner conductors to said one outer surface all comprising precious metals independently selected from a group consisting of gold, silver, platinum, palladium, mixtures thereof and alloys thereof and wherein said thick film via interconnects from said inner conductors to said one outer surface provides electrical connections to said thin film outer conductor.

8. The multilayer low temperature co-fired ceramic structure of claim 7 , wherein said spacings between said lines are less then 10 μm.

9. The multilayer low temperature co-fired ceramic structure of claim 8 , wherein said spacings between said lines are 1-2 μm.

10. The multilayer low temperature co-fired ceramic structure of claim 7 , wherein said thick film inner conductors and said thick film via interconnects between said inner conductors are silver, wherein said thin film outer conductor is gold, and wherein said thick film via interconnects from said inner conductors to said one outer surface are a mixture of silver and gold.

11. The multilayer low temperature co-fired ceramic structure of claim 7 , wherein said thick film inner conductors and said thick film via interconnects between said inner conductors are silver, wherein said thin film outer conductor is gold, and wherein said thick film via interconnects from said inner conductors to said one outer surface are 20-100 wt % gold and 0-80 wt % silver.

12. The multilayer low temperature co-fired ceramic structure of claim 7 , wherein said thick film inner conductors and said thick film via interconnects between said inner conductors, said thin film outer conductors, and said thick film via interconnects from said inner conductors to said one outer surface are all gold.

13. A process for producing a multilayer low temperature co-fired ceramic structure, said process comprising:

a) providing a multilayer low temperature co-fired ceramic comprising glass-ceramic dielectric layers with screen printed thick film inner conductors on portions of said layers and with screen printed thick film via interconnects between said inner conductors and from said inner conductors to the upper and lower outer surfaces of said low temperature co-fired ceramic;

b) polishing said upper and lower outer surfaces;

c) vacuum depositing thin film outer conductors on said polished upper and lower outer surfaces of said low temperature co-fired ceramic; and

d) patterning said thin film outer conductors such that at east a portion of said thin film outer conductors is in the form of lines, wherein the spacings between said lines are less then 50 μm;

said thick film inner conductors and said thick film via interconnects between said inner conductors, said thin film outer conductors, and said thick film via interconnects from said inner conductors to said upper and lower outer surfaces all comprising precious metals independently selected from a group consisting of gold, silver, platinum, palladium, mixtures thereof and alloys thereof and wherein said thick film via interconnects from said inner conductors to said upper and lower outer surfaces provide electrical connections to said thin film outer conductors.

14. The process of claim 13 , wherein said spacings between said lines are less then 10 μm.

15. The process of claim 14 , wherein said spacings between said lines are 1-2 μm.

16. The process of claim 13 , wherein said thick film inner conductors and said thick film via interconnects between said inner conductors are silver, wherein said thin film outer conductors are gold, and wherein said thick film via interconnects from said inner conductors to said upper and lower surfaces are a mixture of silver and gold.

17. The process of claim 13 , wherein said thick film inner conductors and said thick film via interconnects between said inner conductors are silver, wherein said thin film outer conductors are gold, and wherein said thick film via interconnects from said inner conductors to said upper and lower surfaces are 20-100 wt % gold and 0-80 wt % silver.

18. The process of claim 13 , wherein said thick film inner conductors and said thick film via interconnects between said inner conductors, said thin film outer conductors, and said thick film via interconnects from said inner conductors to said upper and lower surfaces are all gold.

19. A process for producing a multilayer low temperature co-fired ceramic structure, said process comprising:

a) providing a multilayer low temperature co-fired ceramic comprising glass-ceramic dielectric layers with screen printed thick film inner conductors on portions of said layers and with screen printed thick film via interconnects between said inner conductors and from said inner conductors to one outer surface of said low temperature co-fired ceramic;

b) polishing said one outer surface;

c) vacuum depositing a thin film outer conductor on said one polished outer surface of said low temperature co-fired ceramic; and

d) patterning said thin film outer conductor such that at least a portion of said thin film outer conductor is in the form of lines, wherein the spacings between said lines are less then 50 μm;

said thick film inner conductors and said thick film via interconnects between said inner conductors, said thin film outer conductor, and said thick film via interconnects from said inner conductors to said one outer surface all comprising precious metals independently selected from a group consisting of gold, silver, platinum, palladium, mixtures thereof and alloys thereof and wherein said thick film via interconnects from said inner conductors to said one outer surface provides electrical connections to said thin film outer conductor.

20. The process of claim 19 , wherein said spacings between said lines are less then 10 μm.

21. The process of claim 20 , wherein said spacings between said lines are 1-2 μm.

22. The process of claim 19 , wherein said thick film inner conductors and said thick film via interconnects between said inner conductors are silver, wherein said thin film outer conductor is gold, and wherein said thick film via interconnects from said inner conductors to said one outer surface are a mixture of silver and gold.

23. The process of claim 19 , wherein said thick film inner conductors and said thick film via interconnects between said inner conductors are silver, wherein said thin film outer conductor is gold, and wherein said thick film via interconnects from said inner conductors to said one outer surface are 20-80 wt % gold and 0-80 wt % silver.

24. The process of claim 19 , wherein said thick film inner conductors and said thick film via interconnects between said inner conductors, said thin film outer conductors, and said thick film via interconnects from said inner conductors to said one outer surface are all gold.

Assignments (4)
CHANGE OF NAME Recorded Mar 20, 2025
From: DU PONT CHINA LIMITED
To: CELANESE MERCURY HOLDINGS INC.
Reel/Frame 070567/0231 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2022
From: DUPONT ELECTRONICS, INC.
To: DU PONT CHINA LIMITED
Reel/Frame 062201/0889 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2019
From: E. I. DU PONT DE NEMOURS AND COMPANY
To: DUPONT ELECTRONICS, INC.
Reel/Frame 049583/0269 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2012
From: GORDON, SCOTT E.; HUGHES, ELIZABETH D.; MALERBI, JOAO CARLOS; NAIR, DEEPUKUMAR M.; HAIR, KUMARAN MANIKANTAN; PARISI, JAMES M.; SMITH, MICHAEL ARNETT; SOUDERS, KEN E.
To: E. I. DU PONT DE NEMOURS AND COMPANY
Reel/Frame 028639/0331 →