IP Library Granted Patent US 9,126,826
Granted Patent B2
US 9,126,826 · App. 13/521,175 · Granted Sep 8, 2015

Micro-electromechanical semiconductor component and method for the production thereof

Inventor: Reinhard Senf (Dortmund, DE)
Assignee: ELMOS Semiconductor AG
B81C1/00158B81B3/007B81B3/0018B81B3/0021B81B3/0072B81B3/0081B81C1/00626G01L9/0047B81B2201/0235B81B2201/0264B81B2203/0127B81C2201/019H01L29/84
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Quick Facts
Patent No.
US 9,126,826
App. No.
13/521,175
Granted
Sep 8, 2015
Kind
B2
Abstract

The micro-electromechanical semiconductor component is provided with a first silicon semiconductor substrate having an upper face, into which a cavity delimited by side walls and a floor wall is introduced, and having a second silicon semiconductor substrate comprising a silicon oxide layer and a polysilicon layer applied thereon having a defined thickness. The polysilicon layer of the second silicon semiconductor substrate faces the upper side of the first silicon semiconductor substrate, the two silicon semiconductor substrates are bonded, and the second silicon semiconductor substrate covers the cavity in the first silicon semiconductor substrate. Grooves that extend up to the polysilicon layer are arranged in the second silicon semiconductor substrate in the region of the section thereof that covers the cavity.

Claims (25)

1. A micro-electromechanical semiconductor component comprising:

a first substrate comprising a silicon layer and a silicon oxide layer applied thereon and forming an upper side of the first silicon semiconductor substrate, wherein in the first substrate there is formed a cavity delimited by side walls as well as a bottom wall and open at the upper side of the first substrate,

a second substrate comprising a silicon oxide layer applied on a silicon layer and a polysilicon layer applied on the silicon oxide layer and having a thickness,

wherein the polysilicon layer of the second substrate is arranged to face the upper side of the first substrate, and is directly bonded to the silicon oxide layer of the first substrate,

wherein the second substrate covers the cavity in the first substrate,

wherein trenches are arranged in the second substrate in a region of a section thereof that covers the cavity,

wherein the trenches are open to a side of the second substrate facing away from the cavity, and

wherein the trenches extend through both the silicon layer and the silicon oxide layer of the second substrate and up to its polysilicon layer.

2. The micro-electromechanical semiconductor component according to claim 1 , wherein the trenches include adjacent trenches separated from each other by bendable webs which extend between a region of the second substrate surrounded by the trenches and a region of the first substrate arranged around the cavity.

3. The micro-electromechanical semiconductor component according to claim 1 , wherein within the section of the second substrate covering the cavity of the first substrate, at least one electric or electronic component is formed that is sensitive to mechanical stresses.

4. A method for producing a micro-electromechanical semiconductor component, the method comprising:

providing a first substrate comprising a silicon layer and a silicon oxide layer applied thereon and forming an upper side of the first silicon substrate,

forming a cavity in the upper side of the first substrate, the cavity being delimited by side walls and a bottom wall in the first substrate,

providing a second substrate comprising a silicon layer, a silicon oxide layer applied on the silicon layer, and a polysilicon layer applied on the silicon oxide layer and having a thickness and forming an upper side of the second substrate,

directly bonding the polysilicon layer of the second substrate to the upper side of the first substrate, and

forming trenches in the second substrate in a section of the second substrate covering the cavity,

wherein the trenches are formed by etching into both the silicon layer and the silicon oxide layer of the second substrate reaching up to its polysilicon layer.

5. A method for producing a micro-electromechanical semiconductor component, the method comprising:

providing a first substrate comprising a silicon layer and a silicon oxide layer applied thereon and forming an upper side of the first substrate,

forming a cavity in the upper side of the first substrate, the cavity being delimited by side walls and a bottom wall in the first substrate,

providing a second substrate comprising a silicon layer, a silicon oxide layer applied on the silicon layer, and a polysilicon layer applied on the silicon oxide layer and having a thickness and forming an upper side of the second substrate,

forming trenches in the second substrate in a section of the second substrate covering the cavity,

wherein the trenches are formed by etching into both the silicon layer and the silicon oxide layer of the second substrate reaching up to its polysilicon layer, and

directly bonding the polysilicon layer of the second silicon semiconductor substrate to the upper side of the first substrate.

6. The method according to claim 4 , wherein within the section of the second substrate covering the cavity, at least one electric or electronic component that is sensitive to mechanical stresses is formed in the substrate.

Assignments (4)
MERGER Recorded Jun 17, 2022
From: SILICON MICROSTRUCTURES, INC.
To: MEASUREMENT SPECIALTIES, INC.
Reel/Frame 060237/0556 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2021
From: ELMOS SEMICONDUCTOR SE
To: SILICON MICROSTRUCTURES, INC.
Reel/Frame 056296/0706 →
CHANGE OF NAME Recorded May 20, 2021
From: ELMOS SEMICONDUCTOR AG
To: ELMOS SEMICONDUCTOR SE
Reel/Frame 056312/0010 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2012
From: SENF, REINHARD
To: ELMOS SEMICONDUCTOR AG
Reel/Frame 029424/0872 →
Priority Claims (1)
EP 10150405 · Jan 11, 2010 · regional
Continuity (1)
Related Publication 20130087866A1 · Apr 11, 2013