IP Library Granted Patent US 8,445,326
Granted Patent B2
US 8,445,326 · App. 13/527,394 · Granted May 21, 2013

Method and system for template assisted wafer bonding

Inventors: John Dallesasse (Geneva, IL); Stephen B. Krasulick (Albuquerque, NM)
Assignee: Skorpios Technologies, Inc.
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Quick Facts
Patent No.
US 8,445,326
App. No.
13/527,394
Granted
May 21, 2013
Kind
B2
Abstract

A method of fabricating a composite semiconductor structure includes providing a substrate including a plurality of devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method further includes providing an assembly substrate, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, aligning the substrate and the assembly substrate, joining the substrate and the assembly substrate to form a composite substrate structure, and removing at least a portion of the assembly substrate from the composite substrate structure.

Claims (41)

1. A method of fabricating a composite semiconductor structure, the method comprising:

providing a substrate including a plurality of devices;

providing a compound semiconductor substrate including a plurality of photonic devices;

dicing the compound semiconductor substrate to provide a plurality of photonic dies, each die including one or more of the plurality of photonics devices;

providing an assembly substrate;

mounting the plurality of photonic dies on predetermined portions of the assembly substrate;

aligning the substrate and the assembly substrate;

joining the substrate and the assembly substrate to form a composite substrate structure; and

removing at least a portion of the assembly substrate from the composite substrate structure.

2. The method of claim 1 wherein the substrate comprises a GaN substrate.

3. The method of claim 1 wherein the plurality of devices comprise CMOS devices.

4. The method of claim 1 wherein the plurality of devices comprise at least one of a detector, a CCD, logic circuits, or emitter coupled logic circuits, BiCMOS circuits, NMOS circuits, or PMOS circuits.

5. The method of claim 1 wherein the compound semiconductor substrate comprises a III-V wafer.

6. The method of claim 5 wherein the plurality of photonic devices comprise at least one of InP photonic devices or GaN photonic devices.

7. The method of claim 1 wherein the compound semiconductor substrate comprises a II-VI wafer.

8. The method of claim 1 wherein the plurality of photonic devices include at least one of a laser, a detector, or a modulator.

9. The method of claim 8 wherein the plurality of photonic devices further include at least one of imaging optics, magnetic materials, birefringent materials, or non-linear optical materials.

10. The method of claim 1 wherein the compound semiconductor substrate further includes electronic devices.

11. The method of claim 10 wherein the electronic devices include at least one of HBTs, HEMTs, or FETs.

12. The method of claim 1 further comprising forming waveguide structures in another portion of the assembly substrate.

13. The method of claim 12 wherein the waveguide structures are operable to optically connect photonic dies of the plurality of photonic dies.

14. The method of claim 1 wherein providing the assembly substrate comprises:

oxidizing a silicon substrate;

implanting the oxidized silicon substrate to form an implant region; and

patterning the implanted substrate to form the predetermined portions.

15. A method of fabricating a composite semiconductor structure, the method comprising:

providing a substrate including a plurality of devices;

providing a compound semiconductor substrate including epitaxial layers;

dicing the compound semiconductor substrate to provide a plurality of compound semiconductor dies;

providing an assembly substrate;

mounting the plurality of compound semiconductor dies on predetermined portions of the assembly substrate;

aligning the substrate and the assembly substrate;

joining the substrate and the assembly substrate to form a composite substrate structure;

removing at least a portion of the assembly substrate from the composite substrate structure;

defining one or more photonic devices on the plurality of compound semiconductor dies; and

patterning electrical interconnects to the one or more photonic devices.

16. The method of claim 15 wherein the plurality of devices comprise CMOS devices.

17. The method of claim 15 wherein the compound semiconductor substrate comprises at least one of a III-V wafer or a II-VI wafer.

18. The method of claim 15 wherein the one or more photonic devices include at least one of a laser, a detector, or a modulator.

19. The method of claim 15 further comprising forming waveguide structures in another portion of the assembly substrate.

20. The method of claim 19 wherein the waveguide structures are operable to optically connect sets of the one or more photonic dies.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 028831 FRAME: 0268. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 4, 2018
From: DALLESASSE, JOHN; KRASULICK, STEPHEN B.
To: SKORPIOS TECHNOLOGIES, INC.
Reel/Frame 045852/0927 →
RELEASE OF SECURITY INTEREST Recorded Nov 22, 2017
From: PACIFIC WESTERN BANK
To: SKORPIOS TECHNOLOGIES, INC.
Reel/Frame 044751/0469 →
SECURITY INTEREST Recorded Oct 23, 2017
From: SKORPIOS TECHNOLOGIES, INC.
To: PACIFIC WESTERN BANK
Reel/Frame 044272/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2012
From: DALLESASSE, JOHN; KRASULICK, STEPHEN B.
To: SKOPRIOS TECHNOLOGIES, INC.
Reel/Frame 028831/0268 →
Continuity (3)
Continuation 13112142 · May 20, 2011
Provisional Application 61420917 · Dec 8, 2010
Related Publication 20120264256A1 · Oct 18, 2012