Shallow trench isolation structures
Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
1. A semiconductor device, comprising:
a silicon-on-insulator (SOI) semiconductor substrate comprising a first silicon layer, a second silicon layer, and a buried oxide layer disposed between the first silicon layer and the second silicon layer;
a high-K gate dielectric layer formed on the first silicon layer;
a shallow trench isolation structure formed in the semiconductor substrate, the shallow trench isolation structure comprising:
a shallow trench formed through the first silicon layer, the buried oxide layer and partially through the second silicon layer;
a first liner formed on exposed surfaces of the first and second silicon layers in the shallow trench;
a second liner conformally lining a bottom and lower sidewalls of the shallow trench, wherein the second liner contacts the first liner and contacts an exposed surface of the buried oxide layer in the shallow trench; and
a trench till material disposed in the shallow trench,
wherein the second liner is formed of a material having etch selectivity with regard to the trench fill material, the second liner being recessed below an upper surface of the first silicon layer to provide a void of the second liner in an upper region of the shallow trench; and
an insulating material filling the void in the upper region of the shallow trench between the first liner and the trench fill material such that the insulating material is in contact with the trench fill material, the second liner and the high-k dielectric layer and isolates the trench fill material and the second liner from the high-k gate dielectric layer.
2. The semiconductor device of claim 1 , wherein the second liner is a high-k dielectric liner.
3. The semiconductor device of claim 1 , wherein the first liner is formed of oxynitride.
4. The semiconductor device of claim 1 , wherein the insulating material is a material that does not conduct an appreciable amount of oxygen.
5. The semiconductor device of claim 1 , wherein the insulating material comprises silicon nitride.
6. The semiconductor device of claim 1 , wherein a thickness of the buried oxide layer is in a range of about 5 nm to about 75 nm.
7. The semiconductor device of claim 1 , wherein the trench till material comprises an oxide material.
8. The semiconductor device of claim 1 , wherein a thickness of the first silicon layer is about 5 nm to about 25 nm.
9. The semiconductor device of claim 1 , wherein the second liner comprises hafnium silicate.
10. The semiconductor device of claim 1 , wherein the second liner comprises hafnium oxide.
11. The semiconductor device of claim 1 , wherein the second liner comprises TiO2.
12. The semiconductor device of claim 1 , wherein the first liner comprises a thermal oxide that is grown on the exposed surfaces of the first and second silicon layers in the shallow trench.