Bump-on-lead flip chip interconnection
View Patent ↗A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.
1. A method of forming a semiconductor device, comprising:
providing a semiconductor die;
forming a plurality of bumps over the semiconductor die;
providing a substrate; and
forming a plurality of conductive traces on the substrate, each trace having an interconnect site for mating to the bumps, the interconnect sites having parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density, wherein the interconnect sites have a width which is less than 1.2 times a width of the conductive trace.
2. The method of claim 1 , wherein one of the bumps has a noncollapsible portion for attaching to a contact pad on the semiconductor die and fusible portion for attaching to the interconnect site.
3. The method of claim 2 , wherein the noncollapsible portion includes lead solder.
4. The method of claim 2 , wherein the fusible portion melts at a temperature which avoids damage to the substrate during reflow.
5. The method of claim 2 , wherein the fusible portion includes eutectic solder.
6. The method of claim 1 , further including disposing an underfill material between the semiconductor die and substrate.
7. The method of claim 1 , wherein the interconnect sites have a width which is less than one-half a diameter of the bump.
8. A method of making a semiconductor device, comprising;
providing a semiconductor die;
forming a bump over the semiconductor die; and
providing a substrate having a conductive trace formed on a die attach surface of the substrate for mating to the bump, the conductive trace having an interconnect site with parallel edges along a length of the conductive trace under the bump from a plan view such that a width of the interconnect site under the bump is no greater than a width of the conductive trace away from the bump.
9. The method of claim 8 , wherein each interconnect bump has a noncollapsible portion including lead solder for attaching to a contact pad on the semiconductor die and fusible portion including eutectic solder for attaching to the interconnect site.
10. The method of claim 9 , wherein the fusible portion melts at a temperature which avoids damage to the substrate during reflow.
11. The method of claim 8 , further including disposing an underfill material between the semiconductor die and substrate.
12. The method of claim 8 , wherein the interconnect sites have a width which is less than one-half a diameter of the bump.
13. A method of making a semiconductor device, comprising;
providing a semiconductor die;
forming a bump over the semiconductor die; and
providing a substrate having a conductive trace formed on a die attach surface of the substrate, the conductive trace having an interconnect site for mating with the bump, the interconnect sites having a width substantially equal to a width of the trace away from the interconnect site.
14. The method of claim 13 , wherein the bump has a noncollapsible portion for attaching to a contact pad on the semiconductor die and fusible portion for attaching to the interconnect site.
15. The method of claim 14 , wherein the fusible portion melts at a temperature which avoids damage to the substrate during reflow.
16. The method of claim 14 , wherein the noncollapsible portion includes lead solder.
17. The method of claim 14 , wherein the fusible portion includes eutectic solder.
18. The method of claim 13 , wherein the interconnect sites have a width which is less than one-half a diameter of the bump.
19. A semiconductor device, comprising:
a semiconductor die;
a plurality of bumps formed over the semiconductor die;
a substrate; and
a plurality of conductive traces formed on the substrate, each trace having an interconnect site for mating to the bumps, the interconnect sites having parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density, wherein the interconnect sites have a width which is less than 1.2 times a width of the conductive trace.
20. The semiconductor device of claim 19 , wherein one of the bumps has a noncollapsible portion for attaching to a contact pad on the semiconductor die and fusible portion for attaching to the interconnect site.
21. The semiconductor device of claim 20 , wherein the noncollapsible portion includes lead solder.
22. The semiconductor device of claim 20 , wherein the fusible portion includes eutectic solder.
23. The semiconductor device of claim 19 , wherein the interconnect sites have a width which is less than one-half a diameter of the bump.