IP Library Granted Patent US 8,846,538
Granted Patent B1
US 8,846,538 · App. 13/560,915 · Granted Sep 30, 2014

Passive elements, articles, packages, semiconductor composites, and methods of manufacturing same

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Quick Facts
Patent No.
US 8,846,538
App. No.
13/560,915
Granted
Sep 30, 2014
Kind
B1
Abstract

Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.

Claims (93)

1. A method for manufacturing a semiconductor article, the method comprising:

forming a first layer of dielectric/polymer material on a substrate;

etching trenches within regions defining a passive element in the first layer;

forming a metal layer on sidewalls of the trenches;

forming a region of dielectric or polymer material over the substrate;

forming areas of the metal layer formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element that are aligned substantially perpendicularly with respect to a primary plane of the substrate; and

defining the regions dedicated for the passive element, wherein the defining includes:

performing a first mask process including formation of a first mask material on the first dielectric/polymer layer;

etching regions of the first dielectric/polymer layer not protected by the first mask material to define regions for formation of the passive element;

stripping the first masking material.

2. The method of claim 1 wherein the first mask process is a 0.18-1 micrometer process and the first mask material is a hard mask material.

3. The method of claim 1 wherein etching the first layer is performed by a process that includes a dry development hard mask.

4. The method of claim 1 wherein the region of dielectric of polymer material is a polyimide layer, and further comprising planarizing the polyimide layer down to the upper surface of the first dielectric/polymer layer, so as to fill the trenches with plug-shaped polyimide material that may be used to create contact regions for electrical connection to components above the substrate.

5. The method of claim 1 further comprising one or both of CMOS and/or Bipolar processes consistent with mix-signal application, whereby the passive element has a high self-resonant frequency and high Q.

6. The method of claim 1 , wherein the first layer is about 3 to about 12 micrometers in thickness.

7. The method of claim 1 , wherein the metal layer is comprised of gold, aluminum and/or copper, and is a layer of about 0.3 um to about 3 um in thickness.

8. The method of claim 1 , wherein the region of dielectric or polymer material is a second dielectric/polymer layer of about 10 to about 20 micrometers in thickness.

9. The method of claim 1 further comprising:

forming an inductive article using the regions defined for the passive element, the inductive article comprising a substrate defined by a primary plane, a first layer of dielectric/polymer material formed on the substrate, the first layer having trenches cut in a direction perpendicular to the primary plane, metal layers formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the inductive element that are aligned substantially perpendicularly with respect to the primary plane, and a region of dielectric or polymer material in the trenches, positioned between the metal layers on the sidewalls.

10. The method of claim 1 further comprising:

forming an capacitive article using the regions defined for the passive element, the capacitive article comprising a substrate defined by a primary plane, a first layer of dielectric/polymer material formed on the substrate, the first layer having trenches cut in a direction substantially perpendicular to the primary plane, planar metal regions formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the capacitive element that are aligned substantially perpendicularly with respect to the primary plane, and a region of dielectric material in the trenches, positioned between the metal layers on the sidewalls.

11. The method of claim 1 further comprising:

forming an resistive article using the regions defined for the passive element, the resistive article substantially comprised of a Titanium or Tantalum base metal material and a nitridation compound including about 30 to about 60 percentage of nitrogen by weight of Titanium or Tantalum, and trace amounts of oxygen introduced into an ambient.

12. The method of claim 2 further comprising:

forming an inductive article using the regions defined for the passive element, the inductive article comprising a substrate defined by a primary plane, a first layer of dielectric/polymer material formed on the substrate, the first layer having trenches cut in a direction perpendicular to the primary plane, metal layers formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the inductive element that are aligned substantially perpendicularly with respect to the primary plane, and a region of dielectric or polymer material in the trenches, positioned between the metal layers on the sidewalls.

13. The method of claim 2 further comprising:

forming an capacitive article using the regions defined for the passive element, the capacitive article comprising a substrate defined by a primary plane, a first layer of dielectric/polymer material formed on the substrate, the first layer having trenches cut in a direction substantially perpendicular to the primary plane, planar metal regions formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the capacitive element that are aligned substantially perpendicularly with respect to the primary plane, and a region of dielectric material in the trenches, positioned between the metal layers on the sidewalls.

14. The method of claim 2 further comprising:

forming an resistive article using the regions defined for the passive element, the resistive article substantially comprised of a Titanium or Tantalum base metal material and a nitridation compound including about 30 to about 60 percentage of nitrogen by weight of Titanium or Tantalum, and trace amounts of oxygen introduced into an ambient.

15. A method for manufacturing a semiconductor article, the method comprising:

forming a first layer of dielectric/polymer material on a substrate;

etching trenches within regions defining a passive element in the first layer;

forming a metal layer on sidewalls of the trenches;

forming a region of dielectric or polymer material over the substrate; and

forming areas of the metal layer formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element that are aligned substantially perpendicularly with respect to a primary plane of the substrate;

wherein etching the first layer is performed by a process that includes a dry development hard mask.

16. The method of claim 15 , wherein the first layer is about 3 to about 12 micrometers in thickness.

17. The method of claim 15 , wherein the metal layer is comprised of gold, aluminum and/or copper, and is a layer of about 0.3 um to about 3 um in thickness.

18. The method of claim 15 , wherein the region of dielectric or polymer material is a second dielectric/polymer layer of about 10 to about 20 micrometers in thickness.

19. The method of claim 15 further comprising:

forming an inductive article using the regions defined for the passive element, the inductive article comprising a substrate defined by a primary plane, a first layer of dielectric/polymer material formed on the substrate, the first layer having trenches cut in a direction perpendicular to the primary plane, metal layers formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the inductive element that are aligned substantially perpendicularly with respect to the primary plane, and a region of dielectric or polymer material in the trenches, positioned between the metal layers on the sidewalls.

20. The method of claim 15 further comprising:

forming an capacitive article using the regions defined for the passive element, the capacitive article comprising a substrate defined by a primary plane, a first layer of dielectric/polymer material formed on the substrate, the first layer having trenches cut in a direction substantially perpendicular to the primary plane, planar metal regions formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the capacitive element that are aligned substantially perpendicularly with respect to the primary plane, and a region of dielectric material in the trenches, positioned between the metal layers on the sidewalls.

21. The method of claim 15 further comprising:

forming an resistive article using the regions defined for the passive element, the resistive article substantially comprised of a Titanium or Tantalum base metal material and a nitridation compound including about 30 to about 60 percentage of nitrogen by weight of Titanium or Tantalum, and trace amounts of oxygen introduced into an ambient.

22. A method for manufacturing a semiconductor article, the method comprising:

forming a first layer of dielectric/polymer material on a substrate;

etching trenches within regions defining a passive element in the first layer;

forming a metal layer on sidewalls of the trenches;

forming a region of dielectric or polymer material over the substrate; and

forming areas of the metal layer formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element that are aligned substantially perpendicularly with respect to a primary plane of the substrate;

wherein the region of dielectric of polymer material is a polyimide layer, and further comprising planarizing the polyimide layer down to the upper surface of the first dielectric/polymer layer, so as to fill the trenches with plug-shaped polyimide material that may be used to create contact regions for electrical connection to components above the substrate.

23. The method of claim 22 , further comprising opening the contact regions for use with wire bonding structures, wherein the contact regions form a landing pad for electrical connection with an external element.

24. The method of claim 22 , wherein the first layer is about 3 to about 12 micrometers in thickness.

25. The method of claim 22 , wherein the metal layer is comprised of gold, aluminum and/or copper, and is a layer of about 0.3 um to about 3 um in thickness.

26. The method of claim 22 , wherein the region of dielectric or polymer material is a second dielectric/polymer layer of about 10 to about 20 micrometers in thickness.

27. The method of claim 22 , further comprising:

forming an inductive article, the inductive article comprising a substrate defined by a primary plane, a first layer of dielectric/polymer material formed on the substrate, the first layer having trenches cut in a direction perpendicular to the primary plane, metal layers formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the inductive element that are aligned substantially perpendicularly with respect to the primary plane, and a region of dielectric or polymer material in the trenches, positioned between the metal layers on the sidewalls.

28. The method of claim 22 , further comprising:

forming a capacitive article, the capacitive article comprising a substrate defined by a primary plane, a first layer of dielectric/polymer material formed on the substrate, the first layer having trenches cut in a direction substantially perpendicular to the primary plane, planar metal regions formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the capacitive element that are aligned substantially perpendicularly with respect to the primary plane, and a region of dielectric material in the trenches, positioned between the metal layers on the sidewalls.

29. The method of claim 22 further comprising:

forming an resistive article using the regions defined for the passive element, the resistive article substantially comprised of a Titanium or Tantalum base metal material and a nitridation compound including about 30 to about 60 percentage of nitrogen by weight of Titanium or Tantalum, and trace amounts of oxygen introduced into an ambient.

30. The method of claim 23 further comprising:

forming an inductive article using the regions defined for the passive element, the inductive article comprising a substrate defined by a primary plane, a first layer of dielectric/polymer material formed on the substrate, the first layer having trenches cut in a direction perpendicular to the primary plane, metal layers formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the inductive element that are aligned substantially perpendicularly with respect to the primary plane, and a region of dielectric or polymer material in the trenches, positioned between the metal layers on the sidewalls.

31. The method of claim 23 further comprising:

forming an capacitive article using the regions defined for the passive element, the capacitive article comprising a substrate defined by a primary plane, a first layer of dielectric/polymer material formed on the substrate, the first layer having trenches cut in a direction substantially perpendicular to the primary plane, planar metal regions formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the capacitive element that are aligned substantially perpendicularly with respect to the primary plane, and a region of dielectric material in the trenches, positioned between the metal layers on the sidewalls.

32. The method of claim 23 further comprising:

forming an resistive article using the regions defined for the passive element, the resistive article substantially comprised of a Titanium or Tantalum base metal material and a nitridation compound including about 30 to about 60 percentage of nitrogen by weight of Titanium or Tantalum, and trace amounts of oxygen introduced into an ambient.

33. A method for manufacturing a semiconductor article, the method comprising:

forming a first layer of dielectric/polymer material on a substrate;

etching trenches within regions defining a passive element in the first layer;

forming a metal layer on sidewalls of the trenches;

forming a region of dielectric or polymer material over the substrate;

forming areas of the metal layer formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element that are aligned substantially perpendicularly with respect to a primary plane of the substrate; and

performing one or both of CMOS and/or Bipolar processes consistent with mix-signal application, whereby the passive element has a high self-resonant frequency and high Q.

34. The method of claim 33 , wherein the first layer is about 3 to about 12 micrometers in thickness.

35. The method of claim 33 , wherein the metal layer is comprised of gold, aluminum and/or copper, and is a layer of about 0.3 um to about 3 um in thickness.

36. The method of claim 33 , wherein the region of dielectric or polymer material is a second dielectric/polymer layer of about 10 to about 20 micrometers in thickness.

37. The method of claims 1 , 2 , 15 , 22 , 23 , 33 , 3 , 5 , 6 , 7 , 16 , 17 , 24 , 25 , 34 , or 35 , wherein the region of dielectric or polymer material is a dielectric comprising a gas.

38. The method of claim 37 , wherein the gas includes air.

39. The method of claim 33 , further comprising:

forming an inductive article, the inductive article comprising a substrate defined by a primary plane, a first layer of dielectric/polymer material formed on the substrate, the first layer having trenches cut in a direction perpendicular to the primary plane, metal layers formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the inductive element that are aligned substantially perpendicularly with respect to the primary plane, and a region of dielectric or polymer material in the trenches, positioned between the metal layers on the sidewalls.

40. The method of claim 33 , further comprising:

forming an capacitive article, the capacitive article comprising a substrate defined by a primary plane, a first layer of dielectric/polymer material formed on the substrate, the first layer having trenches cut in a direction substantially perpendicular to the primary plane, planar metal regions formed on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the capacitive element that are aligned substantially perpendicularly with respect to the primary plane, and a region of dielectric material in the trenches, positioned between the metal layers on the sidewalls.

41. The method of claim 33 further comprising:

forming an resistive article using the regions defined for the passive element, the resistive article substantially comprised of a Titanium or Tantalum base metal material and a nitridation compound including about 30 to about 60 percentage of nitrogen by weight of Titanium or Tantalum, and trace amounts of oxygen introduced into an ambient.

42. The method of claims 9 , 10 , 11 , 12 , 13 , 14 , 19 , 20 , 21 , 27 , 28 , 29 , 30 , 31 , 32 , 39 , 40 or 41 , wherein the region of dielectric or polymer material is a dielectric comprising a gas.

43. The method of claim 42 , wherein the gas includes air.

44. A method of making a Titanium- or Tantalum-based resistor comprising:

sputtering Titanium or Tantalum in a Nitrogen plasma to form an ambient; and

adding a low concentration of oxygen into the ambient.

45. The method of claim 44 , wherein the resistor made by the process substantially comprises TiN x O y , where x is about 1 to about 2, and y is about 0.1 to about 0.3.

46. The method of claim 44 , wherein the resistor made by the process substantially comprises TaN x O y , where x is about 1 to about 2, and y is about 0.1 to about 0.3.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 059687/0344 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: SILICON STORAGE TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0316 →