Patent Assignment
Reel/Frame 059687/0344
Release of Security Interest
Recorded: 2022-02-28
Pages: 46
Assignor
JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Executed: 2022-02-18
Assignee
SILICON STORAGE TECHNOLOGY, INC.
2355 W CHANDLER BLVD, CHANDLER, ARIZONA, 85224
Covered Properties
(384)
Programmable Controlling Device with Non-Volatile Ferroelectric State-Machines for Restarting Processor When Power Is Restored with Execution States Retained in Said Non-Volatile State-Machines on Power Down
Patent:
6,157,979 →
Application:
09/039,299 →
Field Programmable Gate Array (Fpga) Emulator for Debugging Software
Patent:
6,173,419 →
Application:
09/078,872 →
Microcontroller Incorporating an Enhanced Peripheral Controller for Automatic Updating the Configuration Data of Multiple Peripherals by Using a Ferroelectric Memory Array
Patent:
6,145,020 →
Application:
09/078,952 →
Method of Self-Aligning a Floating Gate to a Control Gate and to an Isolation in an Electrically Erasable and Programmable Memory Cell, and a Cell Made Thereby
Patent:
6,369,420 →
Application:
09/110,115 →
Smart Card Comprising Integrated Circuitry Including Eprom and Error Check and Correction System
Patent:
6,108,236 →
Application:
09/118,736 →
Array Architecture and Operating Method for Digital Multilevel Nonvolatile Memory Intergated Circuit System
Patent:
6,282,145 →
Application:
09/231,928 →
Nonvolatile Memory with Self-Aligned Floating Gate and Fabrication Process
Patent:
6,140,182 →
Application:
09/255,360 →
Flash Memory Cell with Self-Aligned Gates and Fabrication Process
Patent:
6,091,104 →
Application:
09/275,670 →
Charge Pump Circuit
Patent:
6,191,642 →
Application:
09/281,570 →
Flash Memory Cell with Thin Floating Gate with Rounded Side Wall
Patent:
6,313,498 →
Application:
09/322,126 →
Voltage Sensing Circuit and Method for Preventing a Low-Voltage from Being Inadvertently Sensed as a High-Voltage During Power-Up or Power-Down
Patent:
6,184,668 →
Application:
09/337,569 →
Flash Memory with Alterable Erase Sector Size
Patent:
6,591,327 →
Application:
09/338,451 →
Memory Cell with Self-Aligned Floating Gate and Separate Select Gate, and Fabrication Process
Patent:
6,222,227 →
Application:
09/370,557 →
Word Line and Source Line Driver Circuitries
Patent:
6,097,636 →
Application:
09/390,060 →
Self Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells and a Memory Array Made Thereby
Patent:
6,329,685 →
Application:
09/401,173 →
Self-Aligned Non-Volatile Random Access Memory Cell and Process to Make the Same
Memory Cell with Self-Aligned Floating Gate and Separate Select Gate, and Fabrication Process
Patent:
6,184,554 →
Application:
09/412,854 →
Memory Management Method and Apparatus for Partitioning Homogeneous Memory and Restricting Access of Installed Applications to Predetermined Memory Ranges
Patent:
6,292,874 →
Application:
09/420,318 →
Flash Memory Cell with Self-Aligned Gates and Fabrication Process
Patent:
6,291,297 →
Application:
09/427,885 →
Clamp Circuit Using Pmos-Transistors with a Weak Temperature Dependency
Patent:
6,242,972 →
Application:
09/428,291 →
An Improved Oscillator and Current Source
Patent:
6,617,935 →
Application:
09/507,219 →
Output stage for a charge pump and a charge pump made thereby
Patent:
6,268,762 →
Application:
09/507,220 →
Method and Apparatus for Testing a Non-Volatile Memory Array Having a Low Number of Output Pins
Patent:
6,560,730 →
Application:
09/507,234 →
Non-volatile flip-flop circuit
Patent:
6,222,765 →
Application:
09/507,570 →
Precision programming of nonvolatile memory cells
Patent:
6,285,598 →
Application:
09/523,828 →
Differential non-volatile content addressable memory cell and array
Patent:
6,639,818 →
Application:
09/527,373 →
Method and Apparatus for Detecting a Tamper Condition and Isolating a Circuit Therefrom
Patent:
6,421,213 →
Application:
09/531,131 →
Isolation circuit and method for controlling discharge of high-voltage in a flash EEPROM
Patent:
6,292,391 →
Application:
09/536,387 →
Reduction of data dependent power supply noise when sensing the state of a memory cell
Patent:
6,219,291 →
Application:
09/561,710 →
Integrated memory circuit having a flash memory array and at least one sram memory array with internal address and data bus for transfer of signals therebetween
Patent:
6,246,634 →
Application:
09/562,490 →
Electronically-eraseable programmable read-only memory having reduced-page-size program and erase
Patent:
6,400,603 →
Application:
09/564,324 →
Voltage regulating circuit with a clamp up circuit and a clamp down circuit operating in tandem
Patent:
6,229,290 →
Application:
09/574,387 →
Flash Memory Cell with Contactless Bit Line, and Process of Fabrication
Patent:
6,426,896 →
Application:
09/576,394 →
Testing of Multilevel Semiconductor Memory
Patent:
6,396,742 →
Application:
09/627,917 →
Bias Generating Circuit for Use with an Oscillating Circuit in an Integrated Circuit Charge Pump
Patent:
6,414,522 →
Application:
09/661,681 →
Timing Independent Current Comparison and Self-Latching Data Circuit
Patent:
6,381,181 →
Application:
09/718,650 →
Power on Circuit for Generating Reset Signal
Integrated Circuit Provided with Meand for Calibrating an Electric Module and Method for Calibrating an Electric Module of an Integrated Circuit
Memory Cell with Self-Aligned Floating Gate and Separate Select Gate, and Fabrication Process
Reduction of Data Dependent Power Supply Noise When Sensing the State of a Memory Cell
On-Chip Method and Apparatus for Testing Semiconductor Circuits
Method of Self-Aligning a Floating Gate to a Control Gate and to an Isolation in an Electrically Erasable and Programmable Memory Cell, and a Cell Made Thereby
Wireless Ic Interconnection Method and System
Control Circuit for a Non-Volatile Memory Array for Controlling the Ramp Rate of High Voltage Applied to the Memory Cells and to Limit the Current Drawn Therefrom
Patent:
6,396,743 →
Application:
09/860,706 →
Flash Memory Cell with Contactless Bit Line, and Process of Fabrication
Array Architecture and Operating Methods for Digital Multilevel Nonvolatile Memory Integrated Circuit System
Method and Apparatus for Sensing a Memory Signal from a Selected Memory Cell of a Memory Device
Patent:
6,456,539 →
Application:
09/903,919 →
Bitline Precharge Matching
Patent:
6,490,212 →
Application:
09/904,160 →
Precision Programming of Nonvolatile Memory Cells
A Self-Aligned Floating Gate Poly for a Flash E2PROM Cell
A Semiconductor Memory Array of Floating Gate Memory Cells with Low Resistance Source Regions and High Source Coupling
Semiconductor Memory Array of Floating Gate Memory Cells with Vertical Control Gate Sidewalls and Insulation Spacers
A Semiconductor Memory Array of Floating Gate Memory Cells with Control Gate Spacer Portions
Self Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Control Gates Protruding Portions, and a Memory Array Made Thereby
Array Architecture and Operating Methods for Digital Multilevel Nonvolatile Memory Integrated Circuit System
Array Architecture and Operating Methods for Digital Multilevel Nonvolatile Memory Integrated Circuit System
Method and Apparatus for Strapping a Plurality of Polysilicon Lines in a Semiconductor Integrated Circuit Device
Patent:
6,455,942 →
Application:
09/930,811 →
A Semiconductor Memory Array of Floating Gate Memory Cells with Floating Gates Having Multiple Sharp Edges
Integrated Circuit for Concurrent Flash Memory with Uneven Array Architecture
Reprogrammable Fuse and Method of Operating
Patent:
6,477,103 →
Application:
09/960,544 →
Folded Cascode High Voltage Operational Amplifier with Class Ab Source Follower Output Stage
Self Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells, and a Memory Array Made Thereby
Semiconductor Memory Array of Floating Gate Memory Cells with Buried Bit-Line and Vertical Word Line Transistor
On-Chip Inductor Using Active Magnetic Energy Recovery
Non-Volatile Flash Fuse Element
System and Method for Providing Asynchronous Sram Functionality with a Dram Array
Electrically-Eraseable Programmable Read-Only Memory Having Reduced-Page-Size Program and Erase
Method and System for Dynamically Clocking Digital Systems Based on Power Usage
Seniconductor Array of Floating Gate Memory Cells and Strap Regions
High Voltage Generation and Regulation System for Digital Multilevel Nonvolatile Memory
Bias Distribution Network for Digital Multilevel Nonvolatile Flash Memory
High Speed Bias Voltage Generating Circuit
Patent:
6,548,995 →
Application:
10/052,278 →
A Semiconductor Memory Array of Floating Gate Memory Cells with Buried Bit-Line and Raised Source Line
Method of Erasing Nonvolatile Tunneling Injector Memory Cell
Patent:
6,580,642 →
Application:
10/135,916 →
Method of Forming a Semiconductor Array of Floating Gate Memory Cells Having Strap Regions and a Peripheral Logic Device Region
Patent:
6,541,324 →
Application:
10/136,797 →
Self Aligned Method of Forming a Semiconductor Array of Non-Volatile Memory Cells
Method and Apparatus for Programming Non-Volatile Memory Cells
Patent:
6,639,842 →
Application:
10/147,959 →
Self Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Horizontally Oriented Edges, and a Memory Array Thereby
An array of floating gate memory cells having strap regions and a peripheral logic device region
High D.C. Voltage to Low D.C. Voltage Circuit Converter
Patent:
6,670,845 →
Application:
10/197,281 →
Method of Forming a Semiconductor Array of Floating Gate Memory Cells and Strap Regions, and a Memory Array and Strap Regions Made Thereby
High Voltage Pulse Method and Apparatus for Digital Multilevel Non-Volatile Memory Integrated System
Wide Dynamic Range and High Speed Voltage Mode Sensing for a Multilevel Digital Non-Volatile Memory
Embedded Recall Apparatus and Method in Nonvolatile Memory
Programmable Serial Interface for a Semiconductor Circuit
Differential Sense Amplifier for Multilevel Non-Volatile Memory
High Speed and High Precision Sensing for Digital Multilevel Non-Volatile Memory System
User Identification for Multi-Purpose Flash Memory
Hybrid Trench Isolation Technology for High Voltage Isolation Using Thin Field Oxide in a Semiconductor Process
Patent:
6,699,772 →
Application:
10/246,882 →
Method for Forming a Sublithographic Opening in a Semiconductor Process
Self-Aligned Split-Gate Nand Flash Memory and Fabrication Process
Flash Memory Cells with Separated Self-Aligned Select and Erase Gates, and Process of Fabrication
Method and Apparatus for Virtually Partitioning an Integrated Multilevel Nonvolatile Memory Circuit
Method and Apparatus for Programming and Testing a Non-Volatile Memory Cell for Storing Multibit States
Method of Utilizing a Plurality of Voltage Pulses to Program Non-Volatile Memory Elements and Related Embedded Memories
Method of Utilizing Voltage Gradients to Guide Dielectric Breakdowns for Non-Volatile Memory Elements and Related Embedded Memories
Non-Volatile Memory Element Integratable with Standard Cmos Circuitry and Related Programming Methods and Embedded Memories
Self Aligned Method of Forming Non-Volatile Memory Cells with Flat Word Line
Digital Multilevel Non-Volatile Memory System
Digital Multilevel Memory System Having Multistage Autozero Sensing
Sub-Volt Sensing for Digital Multilevel Flash Memory
Multistage Autozero Sensing for a Multilevel Non-Volatile Memory Integrated Circuit System
Flash Memory with Trench Select Gate and Fabrication Process
Method and Apparatus for Detecting an Unused State in a Semiconductor Circuit
Self Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Floating Gates Having Multiple Sharp Edges, and a Memory Array Made Thereby
Self Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Control Gate Protruding Portions
Self Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Buried Bit-Line and Raised Source Line, and a Memory Array Made Thereby
Self-Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Buried Source Line and Floating Gate, and a Memory Array Made Thereby
Single Chip Embedded Microcontroller Having Multiple Non-Volatile Erasable Proms Sharing a Single High Voltage Generator
Folded Cascode High Voltage Operational Amplifier with Class Ab Source Follower Output Stage
Method and Apparatus for Detecting Exposure of a Semiconductor Circuit to Ultra-Violet Light
A Semiconductor Memory Array of Floating Gate Memory Cells with Burried Floating Gate and Pointed Channel Region
Self Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Buried Floating Gate, Pointed Floating Gate and Pointed Channel Region, and a Memory Array Made Thereby
Method of Forming a Semiconductor Array of Floating Gate Memory Cells and Strap Regions
Vertical Nrom and Methods for Making Thereof
A Non-Volatile Floating Gate Memory Cell with Floating Gates Formed in Cavities, and Array Thereof, and Method of Formation
Bi-Directional Read/Program Non-Volatile Floating Gate Memory Cell and Array Thereof, and Method of Formation
Bi-Directional Read/Program Non-Volatile Floating Gate Memory Cell with Independent Controllable Control Gates, and Array Thereof, and Method of Formation
Non-Volatile Floating Gate Memory Cell with Floating Gates Formed as Spacers, and an Array Thereof, and a Method of Manufacturing
Method of Planarizing a Semiconductor Die
Patent:
6,703,318 →
Application:
10/423,270 →
Circuit for Compensating Programming Current Required, Depending Upon Programming State
Array of Integrated Circuit Units with Strapping Lines to Prevent Punch Through
High Voltage Shunt Regulator for Flash Memory
Curved Fractional Cmos Bandgap Reference
Column Redundancy for Digital Multilevel Nonvolatile Memory
Phase Change Memory Device Employing Thermal-Electrical Contacts with Narrowing Electrical Current Paths
Method of Manufacturing an Array of Bi-Directional Nonvolatile Memory Cells
Method of Making Sub-Lithographic Sized Contact Holes
Patent:
6,777,260 →
Application:
10/641,490 →
Integrated Circuit with a Reprogrammable Nonvolatile Switch for Selectively Connecting a Source for a Signal to a Circuit
Patent:
6,756,632 →
Application:
10/641,609 →
Integrated Circuit with a Reprogrammable Nonvolatile Switch Having a Dynamic Threshold Voltage (Vth) for Selectively Connecting a Source for a Signal to a Circuit
Patent:
6,809,425 →
Application:
10/641,610 →
Integrated Circuit with a Three Transistor Reprogrammable Nonvolatile Switch for Selectively Connecting a Source for a Signal to a Circuit
Patent:
6,834,009 →
Application:
10/641,803 →
Multi-Bit Rom Cell with Bi-Directional Read and a Method for Making Thereof
Array of Multi-Bit Rom Cells with Each Cell Having Bi-Directional Read and a Method for Making the Array
A Multi-Bit Rom Cell, for Storing One of N>4 Possible States and Having Bi-Directional Read, an Array of Such Cells.
Memory Device Operable with a Plurality of Protocols with Configuration Data Stored in Non-Volatile Storage Elements
Self-Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Buried Floating Gate, and a Memory Array Made Thereby
Phase Change Memory Device Employing Thermally Insulating Voids, and a Method of Making Same
Patent:
6,815,704 →
Application:
10/656,486 →
Memory Device with Discrete Layers of Phase Change Memory Material
Unified Multilevel Cell Memory
Source Synchronous Cdma Bus Interface
Semiconductor Memory Array of Floating Gate Memory Cells with Low Resistance Source Regions and High Source Coupling
Landing Pad for Use as a Contact to a Conductive Spacer
Stacked Gate Memory Cell with Erase to Gate, Array, and Method of Manufacturing
Memory Device and Method of Operating Same
Seek Window Verify Program System and Method for a Multilevel Non-Volatile Memory Integrated Circuit System
Low Voltage Cmos Bandgap Reference
Method of Programming Electrons Onto a Floating Gate of a Non-Volatile Memory Cell
Method of Planarizing a Semiconductor Die
Wide Dynamic Range and High Speed Voltage Mode Sensing for a Multilevel Digital Non-Volatile Memory
Multi-Operational Amplifier System
Self Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Buried Bit-Line and Vertical Word Line Transistor
Circuit and a Method to Screen for Defects in an Addressable Line in a Non-Volatile Memory
Differential Non-Volatile Content Addressable Memory Cell and Array Using Phase Changing Resistor Storage Elements
Patent:
7,050,316 →
Application:
10/797,207 →
Buried Bit Line Non-Volatile Floating Gate Memory Cell with Independent Controllable Control Gate in a Trench, and Array Thereof, and Method of Formation
Flash Memory with Enhanced Program and Erase Coupling and Process of Fabricating the Same
Self-Aligned Split-Gate Nand Flash Memory and Fabrication Process
Method and Apparatus for Compensating for Bitline Leakage Current
Self Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Buried Bit-Line and Raised Source Line
Isolation-Less, Contact-Less Array of Nonvolatile Memory Cells Each Having a Floating Gate for Storage of Charges, and Methods of Manufacturing, and Operating Therefor
Method of Manufacturing an Isolation-Less, Contact-Less Array of Bi-Directional Read/Program Non-Volatile Floating Gate Memory Cells with Independent Controllable Control Gates
Sense Amplifier for Low Voltage High Speed Sensing
Self Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Control Gate Spacers
A Method of Operating a Semiconductor Memory Array of Floating Gate Memory Cells with Horizontally Oriented Edges
Method of Forming Different Oxide Thickness for High Voltage Transistor and Memory Cell Tunnel Dieletric
Semiconductor Memory Array of Floating Gate Memory Cells with Program/Erase and Select Gates
Array Architecture and Operating Methods for Digital Multilevel Nonvolatile Memory Integrated Circuit System
Nand Flash Memory with Nitride Charge Storage Gates and Fabrication Process
Semiconductor Memory Array of Floating Gate Memory Cells with Buried Floating Gate, Pointed Floating Gate and Pointed Channel Region
Non-Volatile Floating Gate Memory Cell with Floating Gates Formed in Cavities, and Array Thereof, and Method of Formation
Integrated Circuit Memory Device with Bit Line Pre-Charging Based Upon Partial Address Decording
High-Speed and Low-Power Differential Non-Volatile Content Addressable Memory Cell and Array
Power Efficient Read Circuit for a Serial Output Memory Device and Method
Non-Planar Non-Volatile Memory Cell with an Erase Gate, an Array Therefor, and a Method of Making Same
Method of Programming a Non-Volatile Memory Cell to Eliminate or to Minimize Program Deceleration
Nrom Device
Phase Change Memory Device Employing Thermally Insulating Voids and Sloped Trench, and a Method of Making Same
Method of Trimming Semiconductor Elements with Electrical Resistance Feedback
High Voltage Generation and Regulation System for Digital Multilevel Nonvolatile Memory
Ring Oscillator for Digital Multilevel Non-Volatile Memory
Test Circuit and Method for Multilevel Cell Flash Memory
Self Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Buried Bit-Line and Raised Source Line, and a Memory Array Made Thereby
Flash Memory with Trench Select Gate and Fabrication Process
Semiconductor Memory and Method of Storing Configuration Data
Self Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Buried Floating Gate and Pointed Channel Region
Nonvolatile Memory Cell Having Floating Gate, Control Gate and Separate Erase Gate, an Array of Such Memory Cells, and Method of Manufacturing
Fast Start Charge Pump for Voltage Regulators
Fast Voltage Regulators for Charge Pumps
Read Bitline Inhibit Method and Apparatus for Voltage Mode Sensing
Patent:
6,992,934 →
Application:
11/080,595 →
Single Transistor Sensing and Double Transistor Sensing for Flash Memory
Dynamically Tunable Resistor or Capacitor Using a Non-Volatile Floating Gate Memory Cell
Bi-Directional Read/Program Non-Volatile Floating Gate Memory Cell and Array Thereof, and Method of Formation
Unified Multilevel Cell Memory
Split Gate Nand Flash Memory Structure and Array, Method of Programming, Erasing and Reading Thereof, and Method of Manufacturing
Bidirectional Split Gate Nand Flash Memory Structure and Array, Method of Programming, Erasing and Reading Thereof, and Method of Manufacturing
Multi-Bit Rom Cell, for Storing One of N>4 Possible States and Having Bi-Directional Read, an Array of Such Cells, and a Method for Making the Array
Self-Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Buried Source Line and Floating Gate
Method and Apparatus for Reducing Operation Disturbance
Unified Multilevel Memory Systems and Methods
Method and Apparatus for Systematic and Random Variation and Mismatch Compensation for Multilevel Flash Memory Operation
Flash Memory Array Having Control/Decode Circuitry for Disabling Top Gates of Defective Memory Cells
Bi-Directional Read/Program Non-Volatile Floating Gate Memory Array, and Method of Formation
Word Line Voltage Boosting Circuit and a Memory Array Incorporating Same
Method of Programming a Non-Volatile Memory Cell
Self-Aligned Split-Gate Nand Flash Memory and Fabrication Process
High Speed and High Precision Sensing for Digital Multilevel Non-Volatile Memory System
Stacked Gate Memory Cell with Erase to Gate, Array, and Method of Manufacturing
Process of Fabricating Flash Memory with Enhanced Program and Erase Coupling
Nor Flash Memory
Method and Apparatus for Testing the Connectivity of a Flash Memory Chip
Method of Programming a Non-Volatile Memory Cell by Controlling the Channel Current During the Rise Period
Bidirectional Split Gate Nand Flash Memory Structure and Array, Method of Programming, Erasing and Reading Thereof, and Method of Manufacturing
Non-Planar Non-Volatile Memory Cell with an Erase Gate, an Array Therefor, and a Method of Making Same
Method of Making a Bi-Directional Read/Program Non-Volatile Floating Gate Memory Cell
Power Line Compensation for Flash Memory Sense Amplifiers
Nand Flash Memory with Densely Packed Memory Gates and Fabrication Process
Self-Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Source Side Erase, and a Memory Array Made Thereby
Method and Apparatus for Strapping Two Polysilicon Lines in a Semiconductor Integrated Circuit Device
Single Transistor Sensing and Double Transistor Sensing for Flash Memory
Multi-Operational Amplifier System
Integrated Flash Memory Systems and Methods for Load Compensation
Method for Handling a Defective Top Gate of a Source-Side Injection Flash Memory Array
Flash Memory Array System Including a Top Gate Memory Cell
High-Speed and Low-Power Differential Non-Volatile Content Addressable Memory Cell and Array
Wide Dynamic Range and High Speed Voltage Mode Sensing for a Multilevel Digital Non-Volatile Memory
Passive Elements, Articles, Packages, Semiconductor Composites, and Methods of Manufacturing Same
Non-Diffusion Junction Split-Gate Nonvolatile Memory Cells and Arrays, Methods of Programming, Erasing, and Reading Thereof, and Methods of Manufacture
Sub Volt Flash Memory System
Assembly of Sim Card and Rfid Antenna
Charge Pump Systems and Methods
Method of Making Phase Change Memory Device Employing Thermally Insulating Voids and Sloped Trench
Chipset for Mobile Wallet System
Split Gate Nand Flash Memory Structure and Array, Method of Programming, Erasing and Reading Thereof, and Method of Manufacturing
Bidirectional Nonvolatile Memory Cell Having Charge Trapping Layer in Trench and an Array of Such Memory Cells, and Method of Manufacturing
Patent:
7,470,949 →
Application:
11/828,213 →
Multi-Operational Amplifier System
Independent Bi-Directional Margin Control Per Level and Independently Expandable Reference Cell Levels for Flash Memory Sensing
Array of Contactless Non-Volatile Memory Cells
Fast Voltage Regulators for Charge Pumps
Sense Amplifier for Low Voltage High Speed Sensing
Semiconductor Memory Array of Floating Gate Memory Cells with Program/Erase and Select Gates
Method of Making a Semiconductor Memory Array of Floating Gate Memory Cells with Program/Erase and Select Gates
Test Circuit and Method for Multilevel Cell Flash Memory
Non-Volatile Memory Device Having High Speed Serial Interface
Method for Erasing a Flash Memory Cell or an Array of Such Cells Having Improved Erase Coupling Ratio
Method of Trimming Semiconductor Elements with Electrical Resistance Feedback
Storage Element for Controlling a Logic Circuit, and a Logic Device Having an Array of Such Storage Elements
Method and Apparatus for Reading and Programming a Non-Volatile Memory Cell in a Virtual Ground Array
Method and Apparatus for Systematic and Random Variation and Mismatch Compensation for Multilevel Flash Memory Operation
High-Speed and Low-Power Differential Non-Volatile Content Addressable Memory Cell and Array
Flash Memory Array System Including a Top Gate Memory Cell
Landing Pad for Use as a Contact to a Conductive Spacer
Flash Memory Array with a Top Gate Line Dynamically Coupled to a Word Line
Non-Volatile Memory Systems and Methods Including Page Read and/or Configuration Features
Non-Volatile Memory Cell with Self Aligned Floating and Erase Gates, and Method of Making Same
Non-Volatile Memory Cell with Buried Select Gate, and Method of Making Same
Fast Voltage Regulators for Charge Pumps
Array and Pitch of Non-Volatile Memory Cells
Array of Non-Volatile Memory Cells Including Embedded Local and Global Reference Cells and System
Programmable Integrated Circuit Having Built in Test Circuit
Patent:
7,786,749 →
Application:
12/468,762 →
Sense Amplifier for Low Voltage High Speed Sensing
Flash Memory Array System Including a Top Gate Memory Cell
Method and Apparatus for Strapping Two Polysilicon Lines in a Semiconductor Integrated Circuit Device
Fin-Fet Non-Volatile Memory Cell, and an Array and Method of Manufacturing
Integrated Flash Memory Systems and Methods for Load Compensation
Charge Pump Circuit and a Novel Capacitor for a Memory Integrated Circuit
Passive Elements, Articles, Packages, Semiconductor Composites, and Methods of Manufacturing Same
Split Gate Non-Volatile Flash Memory Cell Having a Floating Gate, Control Gate, Select Gate and an Erase Gate with an Overhang Over the Floating Gate, Array and Method of Manufacturing
Non-Volatile Memory Device Having High Speed Serial Interface
Method and Apparatus for Testing the Connectivity of a Flash Memory Chip
Test Circuit and Method for Multilevel Cell Flash Memory
Panel Based Lead Frame Packaging Method and Device
Method for Erasing a Flash Memory Cell or an Array of Such Cells Having Improved Erase Coupling Ratio
Non-Volatile Memory Device with Plural Reference Cells, and Method of Setting the Reference Cells
Fast Start Charge Pump for Voltage Regulators
Systems and Methods of Non-Volatile Memory Sensing Including Selective/Differential Threshold Voltage Features
Method of Testing an Integrated Circuit Die, and an Integrated Circuit Die
Power Line Compensation for Flash Memory Sense Amplifiers
Non-Diffusion Junction Split-Gate Nonvolatile Memory Cells and Arrays, Methods of Programming, Erasing, and Reading Thereof, and Methods of Manufacture
Split Gate Nand Flash Memory Structure and Array, Method of Programming, Erasing and Reading Thereof, and Method of Manufacturing
Non-Volatile Memory Element Integratable with Standard Cmos Circuitry
Patent:
8,208,312 →
Application:
12/887,956 →
Multiple Time Programmable Non-Volatile Memory Element
Patent:
8,199,590 →
Application:
12/889,653 →
Method of Sensing a Programmable Non-Volatile Memory Element
Patent:
8,134,859 →
Application:
12/889,659 →
Test Circuit and Method for Multilevel Cell Flash Memory
Integrated Flash Memory Systems and Methods for Load Compensation
Split Gate Non-Volatile Flash Memory Cell Having a Floating Gate, Control Gate, Select Gate and an Erase Gate with an Overhang Over the Floating Gate, Array and Method of Manufacturing
Non-volatile memory systems and methods including page read and/or configuration features
Flash Memory Array System Including a Top Gate Memory Cell
Array of Non-Volatile Memory Cells Including Embedded Local and Global Reference Cells and System
Sense Amplifier for Low Voltage High Speed Sensing
Sub Volt Flash Memory System
Fast Voltage Regulators for Charge Pumps
Charge Pump Systems and Methods
High Endurance Non-Volatile Memory Cell and Array
Sub Volt Flash Memory System
Sense Amplifier for Low Voltage High Speed Sensing
Low Voltage, Low Power Bandgap Circuit
Method of Programming a Split Gate Non-Volatile Floating Gate Memory Cell Having a Separate Erase Gate
Mixed Voltage Non-Volatile Memory Integrated Circuit with Power Saving
Method of Testing Data Retention of a Non-Volatile Memory Cell Having a Floating Gate
Array of Split Gate Non-Volatile Floating Gate Memory Cells Having Improved Strapping of the Coupling Gates
Fast Voltage Regulators for Charge Pumps
Non-volatile Memory Device And A Method Of Programming Such Device
Self-Aligned Stack Gate Structure for Use in a Non-Volatile Memory Array and a Method of Forming Such Structure
Non-Volatile Memory Device and a Method of Operating Same
Method of Operating a Split Gate Flash Memory Cell with Coupling Gate
Non-Volatile Memory Device with Plural Reference Cells, and Method of Setting the Reference Cells
Non-volatile Memory Device With Plural Reference Cells, And Method Of Setting The Reference Cells
Non-volatile Memory Cell Having A High K Dielectric And Metal Gate
Passive Elements, Articles, Packages, Semiconductor Composites, and Methods of Manufacturing Same
Patent:
8,846,538 →
Application:
13/560,915 →
Method of Forming a Memory Cell by Reducing Diffusion of Dopants Under a Gate
Split-Gate Memory Cell With Depletion-Mode Floating Gate Channel, And Method Of Making Same
Self-Aligned Method of Forming a Semiconductor Memory Array of Floating Gate Memory Cells with Single Poly Layer
Split-Gate Memory Cell with Substrate Stressor Region, and Method of Making Same
Non-volatile Memory Array And Method Of Using Same For Fractional Word Programming
Three-Dimensional Flash Memory System
Charge Pump Systems and Methods
Systems and Methods of Non-Volatile Memory Sensing Including Selective/Differential Threshold Voltage Features
Non-volatile Memory Cell Having A Trapping Charge Layer In A Trench And An Array And A Method Of Manufacturing Therefor
Dynamic Programming of Advanced Nanometer Flash Memory
Power Management for a Memory Device
Transistor Design for Use in Advanced Nanometer Flash Memory Devices
Non-Volatile Memory Systems and Methods
Hybrid Chargepump And Regulation Means And Method For Flash Memory Device
High Speed Sensing For Advanced Nanometer Flash Memory Device
Application:
13/958,415 →
Publication:
US 2014/0269061
Split Gate Non-volatile Flash Memory Cell Having A Silicon-Metal Floating Gate And Method Of Making Same
Three-Dimensional Flash NOR Memory System With Configurable Pins
Application:
14/094,595 →
Publication:
US 2015/0155039
Non-volatile Memory Cell Having A Floating Gate And A Coupling Gate With Improved Coupling Ratio Therebetween
Non-volatile Memory Cell With Self Aligned Floating And Erase Gates, And Method Of Making Same
Application:
14/133,821 →
Publication:
US 2015/0179749
Double Patterning Method of Forming Semiconductor Active Areas and Isolation Regions
Low Leakage, Low Threshold Voltage, Split-Gate Flash Cell Operation
Non-Volatile Memory Cells with Enhanced Channel Region Effective Width, and Method of Making Same
Sensing Circuits for Use In Low Power Nanometer Flash Memory Devices
Non-Volatile Memory Program Algorithm Device and Method
Method of Operating a Split Gate Flash Memory Cell with Coupling Gate
Systems and Methods of Non-Volatile Memory Sensing Including Selective/Differential Threshold Voltage Features
A Method of Making a Split Gate Non-Volatile Floating Gate Memory Cell Having a Separate Erase Gate, and a Memory Cell Made Thereby
Non-Volatile Memory Cell with Self Aligned Floating and Erase Gates, and Method of Making Same
Mixed Voltage Non-volatile Memory Integrated Circuit With Power Saving
System And Method To Reduce Disturbances During Programming Of Flash Memory Cells
Power Sequencing for Embedded Flash Memory Devices
Split Gate NAND Flash Memory Structure And Array, Method Of Programming, Erasing And Reading Thereof, And Method Of Manufacturing
Formation Of Self-Aligned Source For Split-Gate Non-volatile Memory Cell
Trimmable Reference Generator For Sense Amplifier
On-The-Fly Trimmable Sense Amplifier
Non-volatile Memory Device With Current Injection Sensing Amplifier
Low Voltage Current Reference Generator for a Sensing Amplifier
Non-volatile Memory Device And A Method Of Programming Such Device
Flash Memory System With EEPROM Functionality
Bitline Regulator For High Speed Flash Memory System
System And Method To Inhibit Erasing Of Portion Of Sector Of Split Gate Flash Memory Cells
Digitally Controlled Delay-Locked Loop Reference Generator
Application:
14/486,694 →
Publication:
US 2016/0006444
Method of Making Embedded Memory Device with Silicon-on-Insulator Substrate
Non-Volatile Split Gate Memory Device and a Method of Operating Same
Non-volatile Memory Array With Concurrently Formed Low and High Voltage Logic Devices
Patent:
9,276,005 →
Application:
14/560,475 →
Geometrically Enhanced Resistive Random Access Memory (RRAM) Cell And Method Of Forming Same
Application:
14/582,089 →
Publication:
US 2016/0181517
Split Gate Non-volatile Flash Memory Cell Having Metal Gates And Method Of Making Same
Split Gate Non-volatile Flash Memory Cell Having Metal-Enhanced Gates And Method Of Making Same
Patent:
9,276,006 →
Application:
14/589,656 →
Flash Memory System Using Complementary Voltage Supplies
Patent:
9,361,995 →
Application:
14/602,262 →
Flash Memory Device Configurable to Provide Read Only Memory Functionality
Array Of Non-volatile Memory Cells With ROM Cells
Method of Making Split-Gate Memory Cell with Substrate Stressor Region
Low Power Operation for Flash Memory System
Split-Gate Flash Memory Cell With Improved Scaling Using Enhanced Lateral Control Gate To Floating Gate Coupling
Dynamic Programming Of Advanced Nanometer Flash Memory
Virtual Ground Non-volatile Memory Array
High Density Split-Gate Memory Cell
Method of Forming Split-Gate Memory Cell Array Along with Low and High Voltage Logic Devices
Method Of Forming Self-Aligned Split-Gate Memory Cell Array With Metal Gates And Logic Devices
Transistor Design for Use in Advanced Nanometer Flash Memory Devices
Method And Apparatus For Inhibiting The Programming Of Unselected Bitlines In A Flash Memory System
Split Gate Non-volatile Memory Cell With 3D FINFET Structure, And Method Of Making Same
Integration Of Split Gate Flash Memory Array And Logic Devices
System and Method for Programming Split-Gate, Non-Volatile Memory Cells
Non-volatile Split Gate Memory Device And A Method Of Operating Same
Application:
15/085,835 →
Publication:
US 2016/0217864
Power Sequencing For Embedded Flash Memory Devices
Method of Forming a Self-Aligned Stack Gate Structure for Use in a Non-Volatile Memory Array
Flash Memory System Using Complementary Voltage Supplies
Sensing Circuit with Sampled Reference Current or Voltage for Flash Memory System
Method Of Forming Split Gate Memory Cells With 5 Volt Logic Devices
Non-volatile Split Gate Memory Cells With Integrated High K Metal Gate Logic Device And Metal-Free Erase Gate, And Method Of Making Same
Split Gate Non-volatile Memory Cell Having A Floating Gate, Word Line, Erase Gate, And Method Of Manufacturing
Method of Programming a Continuous-Channel Flash Memory Device
Array Of Non-volatile Memory Cells With ROM Cells
Application:
15/258,069 →
Publication:
US 2016/0379941
Three-Dimensional Flash Memory System
Self-Aligned Source for Split-Gate Non-Volatile Memory Cell
Related Assignments
(12)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
Feb 10, 2017
From: SILICON STORAGE TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0316 →
Security Interest
Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
Security Interest
Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
Security Interest
Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
Release of Security Interest
May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
Reel/Frame 053466/0011 →
Security Interest
Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
Security Interest
Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
Release of Security Interest
Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
Reel/Frame 059333/0222 →
Release of Security Interest
Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
Reel/Frame 059358/0001 →
Release of Security Interest
Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
Reel/Frame 059863/0400 →
Release of Security Interest
Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
Reel/Frame 059363/0001 →
Release of Security Interest
Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
Reel/Frame 060894/0437 →