Independent bi-directional margin control per level and independently expandable reference cell levels for flash memory sensing
View Patent ↗A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different margins and verify levels.
1. A reference voltage generator comprising:
an absolute read reference level generator providing a plurality of read voltage reference levels in response to a voltage reference;
an absolute read reference level trim decoder providing a first selection signal indicative of an absolute read reference level;
a first multiplexer coupled to the absolute read reference level generator to provide a selected read voltage reference level in response to the first selection signal;
a relative margin level generator providing a plurality of positive margin signals, a plurality of negative margin signals, and a margin reference in response to the voltage reference;
a second multiplexer for selecting ones of said positive margin signals and negative margin signals in response to a second selection signal; and
a relative margin level trimmed decoder providing the second selection signal indicative of a relative margin level.
2. The reference voltage generator of claim 1 wherein the absolute read reference level generator comprises:
an operational amplifier including a first input to receive the voltage reference, including a second input, and including an output;
a current source coupled to the operational amplifier to provide a current thereto in response to a current reference;
a voltage divider coupled between the output of the operational amplifier and a ground node and to the second input of the operational amplifier, and including a plurality of outputs to provide said plurality of read voltage reference levels.
3. The reference voltage generator of claim 2 wherein the voltage divider comprises a plurality of resistors coupled in series between the output of the operational amplifier and the ground node and including terminals coupled to said resistors for providing said plurality of read voltage reference levels and another terminal coupled to the second input of the operational amplifier.
4. The reference voltage generator of claim 1 wherein the absolute read reference level generator comprises:
an operational amplifier including a first input to receive the voltage reference, including a second input, and including an output;
a current source coupled to the operational amplifier to provide a current thereto in response to a current reference; and
first and second voltage dividers, the first voltage divider coupled to the output and the second input of the operational amplifier to control a biased voltage, the second voltage divider mirroring a current in the first voltage divider in response to the biased voltage, the second voltage divider providing the plurality of read voltage reference levels.
5. The reference voltage generator of claim 4 wherein the first voltage divider comprises a first diode connected PMOS transistor, a NMOS transistor, and a plurality of first resistors.
6. The reference voltage generator of claim 1 wherein the absolute read reference level generator comprises:
an operational amplifier including a first input to receive the voltage reference, including a second input, and including an output;
a current source coupled to the operational amplifier to provide a current thereto in response to a current reference;
a voltage divider including a first input coupled to the output of the operational amplifier, including a second input for coupling to ground, including a first output coupled to the second input of the operational amplifier, and including a plurality of second outputs for providing a respective one of a plurality of read reference levels;
wherein said first multiplexer includes a selection circuit including a plurality of inputs coupled to the plurality of second outputs of the voltage divider and includes an output for providing one of said plurality of read reference levels applied to a corresponding input in response to the first selection signal.
7. The reference voltage generator of claim 6 wherein the absolute read reference level further comprises a read reference level trim decoder including an output for providing the first selection signal.
8. The reference voltage generator of claim 1 wherein the relative margin level generator comprises:
an operational amplifier including a first input to receive the voltage reference, including a second input, and including an output;
a current source coupled to the operational amplifier to provide a current thereto in response to a current reference;
a voltage divider coupled between the output of the operational amplifier and a ground node, including a first output coupled to the second input of the operational amplifier to provide a first divided voltage, including a plurality of second outputs for providing a plurality of relative positive margin signals, and including a plurality of third outputs for providing a plurality of relative negative margin signals; and
said second multiplexer includes a selection circuit including a plurality of inputs coupled to respective ones of the pluralities of second and third outputs of the voltage divider and includes an output for providing one of said plurality of relative positive margin signals or one of said plurality of relative negative margin signals in response to the selection signal.
9. The reference voltage generator of claim 8 wherein the relative margin level generator further comprises a trim decoder including an output for providing the selection signal.
10. The reference voltage generator of claim 8 wherein the selection multiplexer comprises:
a third multiplexer providing a selected one of the plurality of relative positive margin signals in response to the second selection signal;
a fourth multiplexer providing a selected one of the plurality of relative negative margin signals in response to a third selection signal; and
a fifth multiplexer providing one of the selected margin signals in response to a fourth selection signal.
11. The reference voltage generator of claim 1 further comprising an absolute read reference level buffer coupled to the first and second multiplexers to provide read reference level in response to a third selection signal.
12. The reference voltage generator of claim 11 wherein the absolute read reference level buffer comprises:
an operational amplifier including a first input, including a second input coupled to receive the voltage reference, and including an output; and
a switching circuit.