Split-gate memory cell with depletion-mode floating gate channel, and method of making same
View Patent ↗A memory device having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and wherein at least a portion of the channel region first portion is of the second conductivity type.
1. A memory device, comprising:
a substrate of semiconductor material of a first conductivity type;
first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween;
a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed partially over the first region and over a first portion of the channel region;
a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed partially or fully over and insulated from a second portion of the channel region;
wherein some or all of the first portion of the channel region is of the second conductivity type, and wherein the second portion of the channel region is entirely of the first conductivity type.
2. The memory device of claim 1 , wherein the second gate has a first portion laterally adjacent to and insulated from the floating gate, and a second portion that extends up and over, and insulated from, the floating gate.
3. The memory device of claim 1 , further comprising:
a conductive program/erase gate laterally to one side of, and insulated from, the floating gate, wherein the program/erase gate is disposed partially or fully over and insulated from the first region; and
the second gate is laterally to an opposite side of the one side of, and insulated from, the floating gate.
4. The memory device of claim 1 , further comprising:
a conductive control gate over and insulated from the floating gate;
a conductive erase gate laterally to one side of, and insulated from, the floating gate, wherein the erase gate is disposed partially or fully over and insulated from the first region; and
the second gate is laterally to an opposite side of the one side of, and insulated from, the floating gate.
5. The memory device of claim 1 , wherein the first conductivity type is P conductivity type, and the second conductivity type is N conductivity type.
6. The memory device of claim 5 , wherein the first and second regions are N+ conductivity type, and the first portion of the channel region is N− conductivity type.
7. A method of forming a memory device, comprising:
providing a substrate of semiconductor material of a first conductivity type;
forming first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, wherein the channel region has first and second portions;
forming a region in the first portion of the channel region having the second conductivity type;
forming a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed partially over the first region and over the first portion of the channel region;
forming a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed partially or fully over and insulated from the second portion of the channel region;
wherein the second portion of the channel region is entirely of the first conductivity type.
8. The method of claim 7 , wherein the second gate has a first portion laterally adjacent to and insulated from the floating gate, and a second portion that extends up and over, and insulated from, the floating gate.
9. The method of claim 7 , further comprising:
forming a conductive program/erase gate laterally to one side of, and insulated from, the floating gate, wherein the program/erase gate is disposed partially or fully over and insulated from the first region; and
the second gate is laterally to an opposite side of the one side of, and insulated from, the floating gate.
10. The method of claim 7 , further comprising:
forming a conductive control gate over and insulated from the floating gate;
forming a conductive erase gate laterally to one side of, and insulated from, the floating gate, wherein the erase gate is disposed partially or fully over and insulated from the first region; and
the second gate is laterally to an opposite side of the one side of, and insulated from, the floating gate.
11. The method of claim 7 , wherein forming of the conductive control gate and the forming of the region in the first portion of the channel region are performed using the same photolithography mask.
12. The method of claim 7 , wherein the forming of the region in the first portion of the channel region having the second conductivity type comprises:
implanting a dopant of the second conductivity type into the region in the first portion of the channel region.
13. The method of claim 7 , wherein the first conductivity type is P conductivity type, and the second conductivity type is N conductivity type.
14. The method of claim 13 , wherein the forming of the region in the first portion of the channel region having the second conductivity type comprises:
implanting an N conductivity type dopant into the region in the first portion of the channel region.
15. The method of claim 13 , wherein the forming of the region in the first portion of the channel region having the second conductivity type comprises:
implanting an N conductivity type dopant into the substrate; and
implanting a P conductivity type dopant into the substrate in a manner that excludes the region in the first portion of the channel region.
16. The method of claim 13 , wherein the first and second regions are N+ conductivity type, and the first portion of the channel region is N− conductivity type.
17. The method of claim 16 , wherein the forming of the region in the first portion of the channel region having the second conductivity type comprises:
implanting an N− conductivity type dopant into the region in the first portion of the channel region.
18. The method of claim 16 , wherein the forming of the region in the first portion of the channel region having the second conductivity type comprises:
implanting an N− conductivity type dopant into the substrate; and
implanting a P conductivity type dopant into the substrate in a manner that excludes the region in the first portion of the channel region.