Granted Patent B2

US 7,544,569 · App. 11/516,431 · Granted Jun 9, 2009

Abstract

Claims (45)

1. A method of erasing a plurality of floating gates arranged in a first row direction in an array of NAND flash memory structures, said array formed in a semiconductor substrate of a first conductivity type and having a plurality of NAND structure with each structure having a first region of a second conductivity type in the substrate; a second region of the second conductivity type in the substrate, spaced apart from the first region in a column direction, forming a channel region therebetween; with the column direction substantially perpendicular to the first row direction; a plurality of floating gates, spaced apart from one another, each insulated from the substrate; each NAND structure further having a control gate insulated from the substrate, the control gate being between a pair of floating gates and being capacitively coupled to the pair of floating gates; with a select gate insulated from the substrate, the select gate being between a pair of floating gates; whereby a floating gate is between a select gate and a control gate, and wherein the NAND structures adjacent to one another in the row direction, have the select gate connected to one another in the row direction, and the control gate connected to one another in the row direction; said method of erasing comprising

applying a negative voltage to a selected row of control gates immediately adjacent to one side of the select plurality of floating gates in the select row; and

applying a positive voltage to a selected row of select gates immediately adjacent to another side of the select plurality of floating gates in the select row;

wherein the first row of floating gates between the selected row of control gate and the selected row of select gates are erased by charges from the first row of floating gates tunneling to the selected row of select gates.

2. The method of claim 1 further comprising applying ground voltage to all the rows of control gates not selected and applying ground voltage to all the rows of select gates not selected.

3. The method of claim 2 further comprising applying a ground voltage to the first region and a ground voltage to the second region.

4. The method of claim 1 further comprising:

applying a negative voltage to a row of control gates immediately adjacent to a side of a second row of floating gates, other than the first row of floating gates, wherein said second row of floating gates is immediately adjacent to the row of select gates to which a positive voltage is applied;

wherein said first row of floating gates and second row of floating gates are erased simultaneously by charges from the first and second rows of floating gates tunneling to the selected row of select gates.

5. A method of erasing a plurality of floating gates arranged in a first row direction in an array of NAND flash memory structures, said array formed in a semiconductor substrate of a first conductivity type and having a plurality of NAND structure with each structure having a first region of a second conductivity type in the substrate; a second region of the second conductivity type in the substrate, spaced apart from the first region in a column direction, forming a channel region therebetween; with the column direction substantially perpendicular to the first row direction; a plurality of floating gates, spaced apart from one another, each insulated from the substrate; each NAND structure further having a control gate insulated from the substrate, the control gate being between a pair of floating gates and being capacitively coupled to the pair of floating gates; with a select gate insulated from the substrate, the select gate being between a pair of floating gates; whereby a floating gate is between a select gate and a control gate, and wherein the NAND structures adjacent to one another in the row direction, have the select gate connected to one another in the row direction, and the control gate connected to one another in the row direction; said method of erasing comprising

applying a negative voltage to a selected row of control gates immediately adjacent to one side of the select plurality of floating gates in the select row; and

applying a positive voltage to the substrate;

wherein the first row of floating gates adjacent to the selected row of control gates are erased by charges from the first row of floating gates tunneling to the substrate.

6. The method of claim 5 further comprising applying ground voltage to all the rows of control gates not selected and applying ground voltage to all the rows of select gates not selected.

7. The method of claim 6 further comprising applying a ground voltage to the first region and a ground voltage to the second region.

8. A method of reading a select floating gate, in an array of NAND flash memory structures, said array formed in a semiconductor substrate of a first conductivity type and having a plurality of NAND structure with each NAND structure having a first region of a second conductivity type in the substrate; a second region of the second conductivity type in the substrate, spaced apart from the first region in a column direction, forming a continuous channel region therebetween; a plurality of floating gates, spaced apart from one another, each insulated from the substrate; each NAND structure further having a control gate insulated from the substrate, the control gate being between a pair of floating gates and being capacitively coupled to the pair of floating gates; with a select gate insulated from the substrate, the select gate being between a pair of floating gates; whereby a floating gate is between a select gate and a control gate, and wherein the NAND structures adjacent to one another in a row direction, have the select gate connected to one another in the row direction, and the control gate connected to one another in the row direction; wherein said row direction is substantially perpendicular to said column direction, said method of reading comprising

applying a first voltage to the first region;

applying a second voltage to each of the control gates other than a first control gate between the two floating gates, one of which is the select floating gate; said second voltage sufficient to turn on the portions of the channel region over which the floating gates, associated with the control gates, are positioned irrespective of the state of the floating gates;

applying the second voltage to each of the select gates, other than the two select gates which are immediately adjacent to the two floating gates of which the first control gate is therebetween;

applying a third voltage to said first control gate; said third voltage sufficient to turn on the portion of the channel region over which the select floating gate is positioned, either strongly or weakly depending upon whether the select floating gate is erased or programmed;

applying the third voltage to the select gate which is immediately adjacent to the select floating gate;

applying a fourth voltage to the select gate which is immediately adjacent to the non-select floating gate which is the floating gate other than the select floating gate that is immediately adjacent to the first control gate; said fourth voltage sufficient to turn on the portion of the channel region over which the non-select floating gate is positioned, irrespective of whether the non-select floating gate is programmed or erased; and

sensing the voltage at the second region to determine the state of said select floating gate.

9. A method of reading a select floating gate, in an array of NAND flash memory structures, said array formed in a semiconductor substrate of a first conductivity type and having a plurality of NAND structure with each NAND structure having a first region of a second conductivity type in the substrate; a second region of the second conductivity type in the substrate, spaced apart from the first region in a column direction, forming a continuous channel region therebetween; a plurality of floating gates, spaced apart from one another, each insulated from the substrate; each NAND structure further having a control gate insulated from the substrate, the control gate being between a pair of floating gates and being capacitively coupled to the pair of floating gates; with a select gate insulated from the substrate, the select gate being between a pair of floating gates; whereby a floating gate is between a select gate and a control gate, and wherein the NAND structures adjacent to one another in a row direction, have the select gate connected to one another in the row direction, and the control gate connected to one another in the row direction; wherein said row direction is substantially perpendicular to said column direction, said method of reading comprising

applying a first voltage to the first region;

applying a second voltage to the second region;

applying a third voltage to each of the control gates other than a first control gate between the two floating gates, one of which is the select floating gate; said third voltage sufficient to turn on the portions of the channel region over which the floating gates, associated with the control gates, are positioned irrespective of the state of the floating gates;

applying a fourth voltage to each of the select gates, other than the two select gates which are immediately adjacent to the two floating gates of which the first control gate is therebetween;

applying a fifth voltage to said first control gate; said fifth voltage sufficient to turn on the portion of the channel region over which the select floating gate is positioned, either strongly or weakly depending upon whether the select floating gate is erased or programmed;

applying the fifth voltage to the select gate which is immediately adjacent to the select floating gate;

applying a sixth voltage to the select gate which is immediately adjacent to the non-select floating gate which is the floating gate other than the select floating gate that is immediately adjacent to the first control gate; said sixth voltage sufficient to turn on the portion of the channel region over which the non-select floating gate is positioned, irrespective of whether the non-select floating gate is programmed or erased; and

sensing the current at the second region to determine the state of said select floating gate.

10. A method of programming a select floating gate in a first NAND structure, in an array of NAND flash memory structures, said array formed in a semiconductor substrate of a first conductivity type and having a plurality of like NAND structure with said first NAND structure having a first region of a second conductivity type in the substrate; a second region of the second conductivity type in the substrate, spaced apart from the first region in a column direction, forming a continuous channel region therebetween; a plurality of floating gates, spaced apart from one another, each insulated from the substrate; said first NAND structure further having a control gate insulated from the substrate, the control gate being between a pair of floating gates and being capacitively coupled to the pair of floating gates; with a select gate insulated from the substrate, the select gate being between a pair of floating gates; whereby a floating gate is between a select gate and a control gate, and wherein the NAND structures adjacent to one another in a row direction, have the select gate connected to one another in the row direction, and the control gate connected to one another in the row direction; wherein said row direction is substantially perpendicular to said column direction, said method of programming comprising:

applying a first voltage to the first region;

applying a second voltage to the second region;

applying a third voltage to each of the control gates other than a first control gate between the two floating gates, one of which is the select floating gate; said third voltage sufficient to turn on the portions of the channel region over which the floating gates, associated with the control gates, are positioned irrespective of the state of the floating gates;

applying a fourth voltage to each of the select gates, other than the two select gates which are immediately adjacent to the two floating gates of which the first control gate is therebetween; said fourth voltage sufficient to turn on the portion of the channel region over which the select gates are position;

applying a fifth voltage to said first control gate; said fifth voltage sufficient to turn on the portion of the channel region over which the select floating gate is positioned;

applying a sixth voltage to the select gate which is immediately adjacent to the select floating gate; said sixth voltage sufficient to turn on the portion of the channel region over which the select gate is positioned, with said sixth voltage lower than said fourth voltage; and

applying a said fourth voltage to the select gate which is immediately adjacent to the non-select floating gate which is the floating gate other than the select floating gate that is immediately adjacent to the first control gate.

11. The method of programming of claim 10 wherein said sixth voltage is applied to the select gate which is to one side of the select floating gate with the first control gate to another side of the select floating gate.

12. The method of programming of claim 11 wherein said first region is to said one side of said select floating gate; and said second region is to said another side of the select floating gate; and

wherein said first voltage is lower than said second voltage.

13. The method of claim 12 wherein said second region of said first NAND structure is connected in common to a second region of a second NAND structure immediately adjacent to the first NAND structure in said row direction.

14. The method of claim 13 further comprising applying a seventh voltage to said first region of said second NAND structure, wherein said seventh voltage is greater than said first voltage but less than said second voltage.

Assignments (14)