Flash memory system using complementary voltage supplies
View Patent ↗A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.
1. A non-volatile memory device comprising:
a semiconductor substrate of a first conductivity type;
an array of non-volatile memory cells in the semiconductor substrate arranged in a plurality of rows and columns, each memory cell comprising:
a first region on a surface of the semiconductor substrate of a second conductivity type;
a second region on the surface of the semiconductor substrate of the second conductivity type;
a channel region between the first region and the second region;
a word line overlying a first portion of the channel region and insulated therefrom, and adjacent to the first region and having little or no overlap with the first region;
a floating gate overlying a second portion of the channel region, adjacent to the first portion, and insulated therefrom and adjacent to the second region;
a coupling gate overlying the floating gate; and
a bit line connected to the first region;
a charge pump circuit for generating a first negative voltage; and
a control circuit for receiving a command signal and for generating a plurality of control signals to control the application of the first negative voltage to the coupling gate of the memory cells.
2. The non-volatile memory device of claim 1 , wherein said plurality of control signals are generated in response to an erase command.
3. The non-volatile memory device of claim 2 , wherein the first negative voltage is between −5 and −9 volts.
4. The non-volatile memory device of claim 1 , wherein said control circuit comprises a negative high voltage level shifter circuit.
5. The non-volatile memory device of claim 4 , wherein said control circuit comprises a negative medium voltage level shifter circuit.
6. The non-volatile memory device of claim 4 , wherein said negative high voltage level shifter circuit generates the first negative voltage.
7. The non-volatile memory device of claim 5 , wherein said negative medium voltage level shifter circuit generates a second negative voltage.
8. The non-volatile memory device of claim 1 , wherein said control circuit comprises a coupling gate decoder circuit.
9. The non-volatile memory device of claim 8 , wherein said coupling gate decoder circuit comprises one or more current limiter circuits.
10. The non-volatile memory device of claim 8 , wherein the coupling gate decoder circuit provides a bias voltage to a coupling gate of an unselected memory cell.
11. The non-volatile memory device of claim 1 , wherein each memory cell is a split gate flash memory cell.
12. The non-volatile memory device of claim 1 , wherein each memory cell is located in a P-well inside a deep N-well.
13. The non-volatile memory device of claim 1 , further comprising a discharge circuit for discharging the first negative voltage.
14. The non-volatile memory device of claim 1 , wherein the charge pump circuit comprises a plurality of pump stages, wherein the bulk of at least one pump stage is coupled to the output of another pump stage.
15. The non-volatile memory device of claim 14 , wherein the charge pump can be configured to generate a negative voltage or a positive voltage.
16. The non-volatile memory device of claim 15 , wherein a deep N-well of a transistor is at zero volts when the charge pump is used to generate a negative voltage and at a positive voltage when the charge pump is used to generate a positive voltage.
17. A method of operating a non-volatile memory device of the type having a semiconductor substrate of a first conductivity type; an array of non-volatile memory cells in the semiconductor substrate arranged in a plurality of rows and columns; with each memory cell having a first region on a surface of the semiconductor substrate of a second conductivity type; a second region on the surface of the semiconductor substrate of the second conductivity type; a channel region between the first region and the second region, a word line overlying a first portion of the channel region and insulated therefrom, and adjacent to the first region and having little or no overlap with the first region; a floating gate overlying a second portion of the channel region, adjacent to the first portion, and insulated therefrom, and adjacent to the second region; a coupling gate overlying the floating gate; a bit line connected to the first region; said method comprising:
applying a first negative voltage to the coupling gate of each of a plurality of memory cells; and
applying a non-negative voltage to the word line, bit line, and second region of each of the memory cells.
18. The method of claim 17 , wherein said method is for erasing the selected memory cell.
19. The method of claim 18 , wherein the first negative voltage is between −5 and −9 volts.
20. The method of claim 17 , wherein the memory device comprises a negative high voltage level shifter circuit.
21. The method of claim 20 , wherein said control circuit comprises a negative medium voltage level shifter circuit.
22. The method of claim 20 , wherein said negative high voltage level shifter circuit generates the first negative voltage.
23. The method of claim 21 , wherein said negative medium voltage level shifter circuit generates a second negative voltage.
24. The method of claim 17 , wherein the memory devices comprises a coupling gate decoder circuit.
25. The method of claim 24 , wherein said coupling gate decoder circuit comprises one or more current limiter circuits.
26. The method of claim 24 , wherein the coupling gate decoder circuit provides a bias voltage to the coupling gates of unselected memory cells.
27. The method of claim 17 , wherein each memory cell is a split gate flash memory cell.
28. The method of claim 17 , further comprising discharging the first negative voltage using a discharge circuit.
29. The method of claim 17 , wherein the charge pump circuit comprises a plurality of pump stages, wherein the bulk of at least one pump stage is coupled to the output of another pump stage.
30. The method of claim 29 , wherein the charge pump can be configured to generate a negative voltage or a positive voltage.
31. The method of claim 30 , further comprising applying zero volts to a deep N-well of a transistor to generate a negative voltage.
32. The method of claim 30 further comprising applying a positive voltage to a deep N-well of a transistor to generate a positive voltage.