Self-aligned method of forming a semiconductor memory array of floating gate memory cells with single poly layer
A method of forming a semiconductor memory cell that includes forming the floating and control gates from the same poly layer. Layers of insulation, conductive and second insulation material are formed over a substrate. A trench is formed in the second insulation material extending down to and exposing the conductive layer. Spacers are formed in the trench, separated by a small and defined gap at a bottom of the trench that exposes a portion of the conductive layer. A trench is then formed through the exposed portion of the conductive layer by performing an anisotropic etch through the gap. The trench is filled with third insulation material. Selected portions of the conductive layer are removed, leaving two blocks thereof separated by the third insulation material.
1. A method of forming a semiconductor memory cell, comprising:
forming a first insulation layer of material on a substrate;
forming a conductive layer of material on the first insulation layer;
forming a second insulation layer of material on the conductive layer;
forming a first trench in the second insulation layer that extends down to and exposes the conductive layer;
forming spacers in the first trench that are separated by a gap at a bottom of the first trench that exposes a portion of the conductive layer;
forming a second trench through the conductive layer by performing an anisotropic etch through the gap;
selectively removing portions of the conductive layer in a manner that leaves first and second blocks of the conductive layer of material which are separated from each other by the second trench;
filling the second trench with an insulation material;
forming first and second spaced-apart regions in the substrate, with a channel region in the substrate therebetween, wherein the first and second regions have a first conductivity type and the channel region has a second conductivity type different from the first conductivity type, and wherein the channel region includes a first portion under the first block and a second portion under the second block; and
after forming the second trench, completely removing the second insulation layer and the spacers.
2. The method of claim 1 , further comprising:
forming a well region in the substrate by implanting a second conductivity type material in the substrate, wherein the first region is formed in the well region.
3. The method of claim 2 , wherein a portion of the second block is disposed over the well region.
4. The method of claim 1 , further comprising:
implanting a material in the substrate to form a well region in the substrate entirely underneath the channel region.
5. The method of claim 1 , further comprising:
forming a spacer of insulation material laterally abutting the first block;
forming a spacer of insulation material laterally abutting the second block.
6. A method of forming a semiconductor memory cell, comprising:
forming a first insulation layer of material on a substrate;
forming a conductive layer of material on the first insulation layer;
forming a second insulation layer of material on the conductive layer;
forming a first trench in the second insulation layer that extends down to and exposes the conductive layer;
forming spacers in the first trench that are separated by a gap at a bottom of the first trench that exposes a portion of the conductive layer;
forming a second trench through the conductive layer by performing an anisotropic etch through the gap;
selectively removing portions of the conductive layer in a manner that leaves first and second blocks of the conductive layer of material which are separated from each other by the second trench;
filling the second trench with an insulation material;
forming first and second spaced-apart regions in the substrate, with a channel region in the substrate therebetween, wherein the first and second regions have a first conductivity type and the channel region has a second conductivity type different from the first conductivity type, and wherein the channel region includes a first portion under the first block and a second portion under the second block;
wherein a lateral edge of the second block is aligned to a lateral edge of the first region.
7. A method of forming a semiconductor memory cell, comprising:
forming a first insulation layer of material on a substrate;
forming a conductive layer of material on the first insulation layer;
forming a second insulation layer of material on the conductive layer;
forming a first trench in the second insulation layer that extends down to and exposes the conductive layer;
forming spacers in the first trench that are separated by a gap at a bottom of the first trench that exposes a portion of the conductive layer;
forming a second trench through the conductive layer by performing an anisotropic etch through the gap;
selectively removing portions of the conductive layer in a manner that leaves first and second blocks of the conductive layer of material which are separated from each other by the second trench;
filling the second trench with an insulation material;
forming first and second spaced-apart regions in the substrate, with a channel region in the substrate therebetween, wherein the first and second regions have a first conductivity type and the channel region has a second conductivity type different from the first conductivity type, and wherein the channel region includes a first pardon under the first block and a second portion under the second block;
wherein a lateral edge of the first block is aligned to a lateral edge of the second region.