Method and apparatus for strapping two polysilicon lines in a semiconductor integrated circuit device
View Patent ↗A method and apparatus for partially strapping two polysilicon lines, each having a first end and second end, uses a metal line having a plurality of spaced apart metal segments with each metal segment partially strapping a different portion of a polysilicon line. The metal segments are arranged from the first end to the second end with the signals propagating from the second end to the first end. Where two metal segments are used, the segments have lengths of x = 2 L 7 and L−X where L is the length between the first end and the second end. Where three segments are used, the segments have lengths of X=0.25L, Y=0.48L, and Z=0.27L.
1. A semiconductor integrated circuit device comprising:
a semiconductor substrate;
a plurality of circuits in said semiconductor substrate;
two substantially parallel, laterally adjacent spaced part polysilicon lines, insulated from said substrate and interconnecting said plurality of circuits; each of said plurality of polysilicon lines having a first end and a second end and having substantially the same length between said first end and said second end with electrical signals traversing from said second end to said first end;
a metal line, spaced apart from said plurality of polysilicon lines, having two segments, with each segment having a length and wherein collectively the length of said two segments is substantially the length from said first end to said second end;
each segment of said metal line for electrically connecting to a different one of said two polysilicon lines;
said metal line arranged from said first end to said second end, with one of the two segments having a length substantially of
x
=
2
L
7
and with the other segment having the length of L−X where L is the length between said first end and said second end.
2. The device of claim 1 wherein said integrated circuit device is a memory device.
3. The device of claim 2 wherein said plurality of polysilicon lines are row lines.
4. The device of claim 3 wherein said device is a volatile memory device.
5. The device of claim 4 wherein said device is a DRAM.
6. The device of claim 4 wherein said device is a SRAM.
7. The device of claim 3 wherein said device is a non-volatile memory device.
8. The device of claim 7 wherein said device is a flash memory device.
9. A semiconductor integrated circuit device comprising:
a semiconductor substrate;
a plurality of circuits in said semiconductor substrate;
two substantially parallel, laterally adjacent spaced part polysilicon lines, insulated from said substrate and interconnecting said plurality of circuits; each of said plurality of polysilicon lines having a first end and a second end and having substantially the same length between said first end and said second end with electrical signals traversing from said second end to said first end;
a metal line, spaced apart from said plurality of polysilicon lines, having three segments, with each segment having a length and wherein collectively the length of said three segments is substantially the length from said first end to said second end;
each segment of said metal line for electrically connecting to a different portion of one of the two polysilicon lines;
said metal line arranged from said first end to said second end, with the length of the segments substantially
X=0.25L
Y=0.48L
Z=0.27L
where L is the length between said first end and said second end.
10. The device of claim 9 wherein said integrated circuit device is a memory device.
11. The device of claim 10 wherein said plurality of polysilicon lines are row lines.
12. The device of claim 11 wherein said device is a volatile memory device.
13. The device of claim 12 wherein said device is a DRAM.
14. The device of claim 12 wherein said device is a SRAM.
15. The device of claim 11 wherein said device is a non-volatile memory device.
16. The device of claim 15 wherein said device is a flash memory device.