Bi-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation
View Patent ↗A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. An independently controllable control gate is insulated from each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. The independently controllable control gates permit an array of such memory cells to operate in a NAND configuration.
1. A non-volatile memory cell for the storage of a plurality of bits, comprising:
a substantially single crystalline semiconductive substrate material of a first conductivity type, having a substantially planar surface;
a first trench in said substrate; said first trench having a side wall, substantially perpendicular to the planar surface, and a bottom wall;
a second trench in said substrate; spaced apart from said first trench, said second trench having a side wall, substantially perpendicular to the planar surface, and a bottom wall;
a first region of a second conductivity type, different from said first conductivity type in said material, along the bottom wall of said first trench;
a second region of said second conductivity type in said material, spaced apart from said first region, along the bottom wall of said second trench;
a channel region, having a first portion, a second portion and a third portion, connecting said first and second regions for the conduction of charges, said first portion being along the side wall of said first trench, said second portion being along the side wall of said second trench;
a dielectric on said channel region;
a first floating gate on said dielectric, spaced apart from said first portion of said channel region; said first portion of said channel region adjacent to said first region, said first floating gate for the storage of at least one of said plurality of bits;
a second floating gate on said dielectric, spaced apart from said second portion of said channel region; said second portion of said channel region adjacent to said second region, said second floating gate for the storage of at least another of said plurality of bits;
a gate electrode on said dielectric, spaced apart from said third portion of said channel region, said third portion of said channel region between said first portion and said second portion;
a first independently controllable gate electrode, in said first trench, capacitively coupled to said first floating gate and insulated from said first region; and
a second independently controllable gate electrode, in said second trench, capacitively coupled to said second floating gate and insulated from said second region.
2. The cell of claim 1 wherein said substantially single crystalline semiconductive substrate material is single crystalline silicon having a planar surface.
3. The cell of claim 1 wherein said first floating gate has a tip portion that is substantially perpendicular to said gate electrode.
4. The cell of claim 3 wherein said second floating gate has a tip portion that is substantially perpendicular to said gate electrode.
5. An array of non-volatile memory cells, arranged in a plurality of rows and columns, said array comprising:
a substantially single crystalline semiconductive substrate material of a first conductivity type, having a planar surface;
a plurality of spaced apart trenches, substantially parallel to one another in said substrate, each trench having a side wall, substantially perpendicular to the planar surface, and a bottom wall;
a plurality of non-volatile memory cells arranged in a plurality of rows and columns in said semiconductive substrate material with each cell for storing a plurality of bits, and with each cell comprising:
a first region of a second conductivity type, different from said first conductivity type in said material, along the bottom wall of a first trench;
a second region of said second conductivity type in said material, along the bottom wall of a second trench;
a channel region, having a first portion, a second portion and a third portion, connecting said first and second regions for the conduction of charges, said first portion being along the side wall of a first trench, said second portion being along the side wall of a second trench, said third portion being along the planar surface of the substrate between said first and second portions; a dielectric on said channel region;
a first floating gate on said dielectric, in the first trench, spaced apart from said first portion of said channel region; said first portion of said channel region adjacent to said first region, said first floating gate for the storage of at least one of said plurality of bits;
a second floating gate on said dielectric, in the second trench, spaced apart from said second portion of said channel region; said second portion of said channel region adjacent to said second region, said second floating gate for the storage of at least another of said plurality of bits; a gate electrode on said dielectric, spaced apart from said third portion of said channel region;
a first independently controllable gate electrode, in the first trench, capacitively coupled to said first floating gate, and insulated from said first region; and
a second independently controllable gate electrode, in the second trench, capacitively coupled to said second floating gate, and insulated from the second region;
wherein said cells in the same row have said gate electrode in common;
wherein said cells in the same column have said first region in common, said second region in common, said first independently controllable gate electrode in common, and said second independently controllable gate electrode in common; and
wherein said cell in adjacent columns have said first region in common and said first independently controllable gate electrode in common.
6. The array of claim 5 wherein said substantially single crystalline semiconductive substrate material is single crystalline silicon having a planar surface.
7. The array of claim 5 wherein said first floating gate has a tip portion that is substantially perpendicular to said gate electrode.
8. The array of claim 7 wherein said second floating gate has a tip portion that is substantially perpendicular to said gate electrode.