Bitline regulator for high speed flash memory system
View Patent ↗A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage.
1. A memory system, comprising:
an array of memory cells organized into rows and columns, wherein each column of memory cells is coupled to a bit line; and
a bitline regulator for applying a bias voltage to each bit line, the bitline regulator comprising:
a first circuit for outputting a plurality of trim bits; and
a second circuit adjusting the bias voltage in response to the plurality of trim bits; wherein the first circuit comprises:
a sample and hold circuit for generating a sampled voltage based on the bias voltage;
a comparator for comparing the sampled voltage to a reference voltage and generating an output; and
an arbiter for receiving the output from the comparator and generating the trim bits.
2. The memory system of claim 1 , wherein the first circuit generates the trim bits based upon a comparison of the bias voltage to a reference voltage.
3. The memory system of claim 1 , wherein the second circuit comprises:
a boost circuit for adjusting the output strength in response to one of the trim bits.
4. The memory system of claim 3 , wherein the second circuit comprises:
a plurality of boost circuits, each responsive to a trim bit, for adjusting the output strength.
5. The memory system of claim 3 , wherein the second circuit further comprises:
a control signal for enabling the boost circuit.
6. The memory system of claim 4 , wherein the second circuit further comprises:
a control signal for enabling the plurality of boost circuits.
7. The memory system of claim 1 , wherein the memory cells comprise flash memory cells.
8. A memory system, comprising:
an array of memory cells organized into rows and columns, wherein each column of memory cells is coupled to a bit line; and
a bitline regulator for applying a bias voltage to each bit line, the bitline regulator comprising:
a sample and hold circuit for generating a sampled voltage based on the bias voltage;
a comparator for comparing the sampled voltage to a reference voltage and generating an output;
an arbiter for receiving the output from the comparator and generating trim bits; and
a boost circuit for adjusting the output strength in response to one or more of the trim bits.
9. The memory system of claim 8 , wherein the memory cells comprise flash memory cells.
10. The memory system of claim 8 , wherein the trim bits comprise eight bits.
11. The memory system of claim 8 , wherein the reference voltage is 1.0 volts.
12. The memory system of claim 8 , wherein the arbiter comprises a controller.
13. The memory system of claim 8 , wherein the arbiter comprises discrete logic.
14. A method of adjusting a bias voltage of a bitline in a memory system, comprising:
sampling a voltage of the bitline to generate a sampled voltage;
comparing the sampled voltage to a reference voltage to generate an output;
generating, from within the memory system, a plurality of trim bits in response to the output; and
changing the bias voltage in response to the plurality of trim bits.
15. The method of claim 14 , wherein the changing step is performed by a bitline regulator.
16. The method of claim 14 , wherein the changing step comprises coupling one or more boost circuits to the bitline.
17. The method of claim 14 , wherein the changing step is enabled by a control signal.
18. The method of claim 14 , wherein the reference voltage is 1.0 volts.
19. The method of claim 14 , further comprising using the bitline to read a memory cell.