Sense amplifier for low voltage high speed sensing
View Patent ↗A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
1. A sense amplifier comprising
a comparator including a first input coupled to a reference voltage node, a second input coupled to a data voltage node, and an output providing a signal indicative of a difference in voltages on the reference and data voltage nodes;
a first load circuit coupled to the reference voltage node to load a reference cell;
a second load circuit coupled to the data voltage node to load a data cell;
an impedance circuit coupled to the first input, the impedance circuit comprising:
a switch coupled to a supply voltage node; and
a voltage divider coupled between the switch and ground, the voltage divider including:
a first resistor including a first terminal coupled to the switch and including a second terminal coupled to the first input of the comparator; and
a second resistor including a first terminal coupled to the second terminal of the first resistor and including a second terminal coupled to a ground node; and
wherein the switch, when disabled, sets the impedance circuit at an impedance established by the voltage divider that is a higher impedance relative to an impedance of the impedance circuit when the switch is enabled.
2. The sense amplifier of claim 1 wherein the first load circuit includes a PMOS transistor including a source terminal coupled to a supply voltage terminal, including a drain coupled to the reference voltage node, and including a gate coupled to a control signal node,
wherein the second load circuit comprises a reference current source.
3. The sense amplifier of claim 2 further comprising a first switch coupled between the first and second inputs of the comparator to selectively couple said first and second inputs.
4. The sense amplifier of claim 1 wherein the first load circuit is disposed adjacent said reference cell, the second load circuit is disposed adjacent said data cell.
5. The sense amplifier of claim 4 wherein the reference cell is disposed outside of an array that includes the data cell.
6. The sense amplifier of claim 1 wherein the switch comprises:
a MOS transistor including first and second terminals spaced apart with a channel therebetween and including a gate for controlling current in said channel, said first terminal being coupled to a supply voltage node, said second terminal being coupled to the first terminal of the second resistor, said gate being coupled to a reference supply voltage node.
7. The sense amplifier of claim 6 wherein the impedance circuit further comprises a filter coupled between the reference supply voltage node and the gate of the MOS transistor.
8. The sense amplifier of claim 1 further comprising a control circuit coupled to the first and second load circuits to control the loading on the reference voltage node and the data reference nodes, respectively, in response to voltages on the reference and data voltage nodes.
9. The sense amplifier of claim 1 wherein the impedance circuit comprises a resistor divider composed of a third resistor and a fourth resistor.
10. The sense amplifier of claim 1 further comprising a first switch coupled between the first and second inputs of the comparator to selectively couple said first and second inputs.
11. A sense amplifier comprising:
a comparator including a first input coupled to a reference voltage node, a second input coupled to a data voltage node, and an output providing a signal indicative of a difference in voltages on the reference and data voltage nodes;
a first load circuit coupled to the reference voltage node to load a reference cell;
a second load circuit coupled to the data voltage node to load a data cell;
an impedance circuit coupled to the first input, the impedance circuit comprising:
a switch coupled to a supply voltage node;
a first resistor including a first terminal coupled to the switch and including a second terminal coupled to the first input of the comparator;
a second resistor including a first terminal coupled to the second terminal of the first resistor and including a second terminal coupled to a ground node, wherein together the switch, the first resistor and the second resistor form a first voltage divider; and
a second voltage divider coupled between the switch and ground and having a node connected to the first terminal of the second resistor;
wherein the switch, when disabled, sets the impedance circuit at an impedance established by the second voltage divider that is a higher impedance relative to an impedance of the impedance circuit when the switch is enabled.
12. The sense amplifier of claim 11 further comprising a second switch coupled between the first and second inputs of the comparator to selectively couple said first and second inputs.
13. The sense amplifier of claim 11 wherein the first load circuit includes a PMOS transistor including a source terminal coupled to a supply voltage terminal, including a drain coupled to the reference voltage node, and including a gate coupled to a control signal node, and
wherein the second load circuit comprises a reference current source.
14. The sense amplifier of claim 13 further comprising a second switch coupled between the first and second inputs of the comparator to selectively couple said first and second inputs.
15. The sense amplifier of claim 11 wherein the first load circuit is disposed adjacent said reference cell, the second load circuit is disposed adjacent said data cell.
16. The sense amplifier of claim 15 wherein the reference cell is disposed outside of an array that includes the data cell.
17. The sense amplifier of claim 11 wherein the first voltage divider applies a voltage to the reference voltage line.
18. The sense amplifier of claim 11 further comprising a capacitor coupled to the comparator to hold a reference voltage level of the comparator during sensing.
19. A sense amplifier comprising:
a comparator including a first input coupled to a reference voltage node, a second input coupled to a data voltage node, and an output providing a signal indicative of a difference in voltages on the reference and data voltage nodes;
a first load circuit coupled to the reference voltage node to load a reference cell;
a second load circuit coupled to the data voltage node to load a data cell;
an impedance circuit coupled to the first input, the impedance circuit comprising:
a switch coupled to a supply voltage node; and
a voltage divider coupled between the switch and ground, the voltage divider including:
a first resistor including a first terminal coupled to the switch and including a second terminal coupled to the first input of the comparator; and
a second resistor including a first terminal coupled to the second terminal of the first resistor and including a second terminal coupled to a ground node; and
a filter circuit that applies a filtered bias voltage to the switch; and
a holding circuit including a capacitor coupled between the first input of the comparator and a ground node, the holding circuit configured to maintain the voltage on the first input of the comparator.
20. The sense amplifier of claim 19 wherein the first load circuit is disposed adjacent said reference cell, the second load circuit is disposed adjacent said data cell.
21. The sense amplifier of claim 20 wherein the reference cell is disposed outside of an array that includes the data cell.
22. The sense amplifier of claim 19 further comprising a first switch coupled between the first and second inputs of the comparator to selectively couple said first and second inputs.
23. The sense amplifier of claim 19 wherein the MOS transistor is an NMOS transistor.
24. The sense amplifier of claim 19 wherein the switch is a MOS transistor and the filter is coupled between the reference supply voltage node and the gate of the MOS transistor.
25. The sense amplifier of claim 23 wherein the NMOS transistor has a gate threshold of about −0.1 to about 0.3 volts.
26. The sense amplifier of claim 23 wherein the NMOS transistor is a native NMOS transistor.
27. The sense amplifier of claim 26 wherein the native NMOS transistor has a gate threshold of about −0.1 to about 0.3 volts.
28. The sense amplifier of claim 23 wherein the NMOS transistor is configured to isolate noise of a supply voltage from the reference voltage line.
29. The sense amplifier of claim 23 wherein the filter circuit is coupled between a reference voltage and the impedance circuit.
30. The sense amplifier of claim 29 wherein the filter circuit generates a filtered bias voltage applied to a gate of the NMOS transistor.
31. The sense amplifier of claim 29 wherein the filter circuit comprises a resistor coupled between the reference voltage and an output connected to the impedance circuit and a capacitor coupled between the output and ground.
32. The sense amplifier of claim 19 wherein the voltage divider applies a voltage to the reference voltage line.
33. The sense amplifier of claim 26 further comprising a switch coupled between the first and second inputs of the comparator to selectively couple said first and second inputs.