Mixed voltage non-volatile memory integrated circuit with power saving
An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage and is generated by a voltage regulator that receives the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. The voltage regulator is enabled by a controller.
1. An integrated circuit flash memory system comprising:
a memory flash array;
a first die pad receiving a first voltage;
a first circuit connected to the first die pad;
a second die pad receiving a second voltage;
a second circuit connected to the second die pad; and
a power sequence controller to provide configuration bits to configure the first circuit in response to a voltage from a first power supply exceeding a first voltage threshold during a power up sequence, the second circuit in response to a voltage from a second power supply exceeding a second voltage threshold during the power up sequence, and the connections of the first die pad and the second die pad.
2. The system of claim 1 , wherein the controller is configured to provide the configuration bits during the power up sequence.
3. The system of claim 2 , wherein said power up sequence includes concurrent pattern checking.
4. The system of claim 1 , wherein said configuration bits control different power saving modes for erase, program, read, standby, and deep power down with hard and soft regulation power level for the first circuit and the second circuit.
5. An integrated circuit flash memory system comprising:
a bond pad for receiving a first voltage;
a first die pad coupled to the bond pad;
a first circuit coupled to the first die pad, the first circuit comprising a voltage regulator for receiving the first voltage and generating a second voltage as an output, wherein the second voltage is lower than the first voltage;
a second die pad coupled to the output of the voltage regulator;
a second circuit coupled to the second die pad and the output of the voltage regulator, the second circuit comprising a memory flash array; and
a controller for enabling the voltage regulator in response to detection of current flow from the second die pad to the second circuit.
6. The system of claim 5 , wherein the first voltage is 3.0 volts.
7. The system of claim 6 , wherein the second voltage is 1.8 volts.
8. The system of claim 5 , wherein the voltage regulator comprises a DC-DC regulator.
9. The system of claim 8 , wherein the first circuit comprises an TO buffer circuit.
10. The system of claim 9 , wherein the first circuit comprises a charge pump circuit.
11. The system of claim 5 , wherein the controller is configured to provide a configuration bit to enable the voltage regulator.
12. The system of claim 5 , wherein the controller is configured to perform a power-up sequence.
13. The system of claim 12 , wherein the controller is configured to perform a fixed pattern check during the power-up sequence.
14. A method of controlling a flash memory system, comprising:
generating, by a controller, a configuration bit;
enabling a voltage regulator using the configuration bit;
receiving, by the voltage regulator, a first voltage from a first die pad; and
providing, by the voltage regulator, a second voltage to a second die pad and a flash memory array, wherein the second voltage is lower than the first voltage;
wherein the generating step occurs in response to the detection of current flow from the second die pad to a circuit coupled to the second die pad.
15. The method of claim 14 , wherein the first voltage is 3.0 volts.
16. The method of claim 15 , wherein the second voltage is 1.8 volts.
17. The method of claim 14 , wherein the voltage regulator comprises a DC-DC regulator.
18. The method of claim 14 , further comprising: performing, by the controller, a power-up sequence.
19. The method of claim 18 , wherein the performing step comprises: performing, by the controller, a fixed pattern check.
20. The method of claim 18 , wherein the performing step comprises: monitoring, by the controller, the status of the first voltage.