Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby
View Patent ↗A method of forming an array of floating gate memory cells, and an array formed thereby, that includes source and drain regions formed in a substrate, and a conductive block of material disposed over the source region. The floating gate is formed as a thin, L-shaped layer of conductive material having a first portion disposed over the channel region and a second portion extending vertically along the conductive block. The control gate includes a first portion disposed adjacent to and insulated from a distal end of the floating gate first portion, and a second portion disposed adjacent to the channel region. A portion of the control gate could extend into a trench formed into the substrate, wherein the drain region is formed underneath the trench, and the channel region has a first portion extending along the trench sidewall and a second portion extending along the substrate surface.
1. An electrically programmable and erasable memory device comprising:
a substrate of semiconductor material having a first conductivity type and a surface;
first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having a first portion and a second portion;
an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region;
an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion; and
a block of conductive material disposed over and electrically connected to the first region, wherein the floating gate second portion extends along and is insulated from a surface of the conductive material block;
wherein the control gate includes a first portion disposed adjacent to and insulated from a distal end of the floating gate first portion, and a second portion disposed adjacent to and insulated from the channel region first portion; and
wherein the control gate further includes a third portion that is disposed over and insulated from a distal end of the floating gate second portion.
2. The device of claim 1 , further comprising:
a spacer of insulating material disposed over the floating gate first portion and laterally adjacent to the floating gate second portion.
3. An electrically programmable and erasable memory device comprising:
a substrate of semiconductor material having a first conductivity type and a surface;
first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having a first portion and a second portion;
an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region;
an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion; and
a trench formed into the substrate surface, wherein the second region is formed underneath the trench, and wherein the channel region first portion extends substantially along a sidewall of the trench and the channel region second portion extends substantially along the surface of the substrate;
wherein each of the floating gate first and second elongated portions has a distal end that terminates in a thin tip portion the directly faces and is insulated from the control gate.
4. The device of claim 3 , wherein the control gate includes a first portion disposed adjacent to and insulated from a distal end of the floating gate first portion, and a second portion extending into the trench and disposed adjacent to and insulated from the channel region first portion.
5. The device of claim 3 , wherein the channel region further includes a third portion that extends underneath at least a portion of the trench.
6. The device of claim 3 , wherein the channel region first and second portions are non-linear with respect to each other, with the channel region first portion extending in a direction directly toward the floating gate first portion to define a path for programming the floating gate.
7. An electrically programmable and erasable memory device comprising:
a substrate of semiconductor material having a first conductivity type and a surface;
first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having a first portion and a second portion;
an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region;
an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion; and
a trench formed into the substrate surface, wherein the first region is formed underneath the trench, and wherein the channel region second portion extends substantially along a sidewall of the trench and the channel region first portion extends substantially along the surface of the substrate;
wherein each of the floating gate first and second elongated portions has a distal end that terminates in a thin tip portion the directly faces and is insulated from the control gate.
8. An electrically programmable and erasable memory device comprising:
a substrate of semiconductor material having a first conductivity type and a surface;
first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having a first portion and a second portion;
an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region;
an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion; and
a trench formed into the substrate surface, wherein the first region is formed underneath the trench, and wherein the channel region second portion extends substantially along a sidewall of the trench and the channel region first portion extends substantially along the surface of the substrate;
wherein the floating gate second portion extends over and is insulated from a bottom surface of the trench, and wherein the floating gate first portion extends along and is insulated from the sidewall of the trench.
9. The device of claim 8 , wherein the floating gate first portion includes an upper segment that extends above the substrate surface, and wherein the control gate is disposed laterally adjacent to and insulated from the floating gate upper segment.
10. The device of claim 9 , wherein the control gate includes a portion disposed over and insulated from a distal end of the floating gate upper segment.
11. An electrically programmable and erasable memory device comprising:
a substrate of semiconductor material having a first conductivity type and a surface;
first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having a first portion and a second portion;
an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region;
an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion;
a trench formed into the substrate surface, wherein the first region is formed underneath the trench, and wherein the channel region second portion extends substantially along a sidewall of the trench and the channel region first portion extends substantially along the surface of the substrate; and
a block of conductive material having at least a lower portion thereof disposed in the trench laterally adjacent to and insulated from the floating gate.
12. The device of claim 11 , wherein the lower portion of the conductive material block is disposed over and insulated from the first region.
13. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material having a first conductivity type and a surface;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
each of the active regions including a plurality of memory cells, each of the memory cells comprising:
first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having first and second portions,
an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region, and
an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion;
wherein each of the floating gate first and second elongated portions has a distal end that terminates in a thin tip portion the directly faces and is insulated from the control gate;
wherein each of the floating gate second portions extends in a direction substantially perpendicular to the substrate surface.
14. The array of claim 13 , wherein each of the floating gates is substantially L-shaped.
15. The array of claim 14 , wherein each of the channel regions is substantially linear.
16. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material having a first conductivity type and a surface;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
each of the active regions including a plurality of memory cells, each of the memory cells comprising:
first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having first and second portions,
an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region, and
an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion; and
a plurality of trenches formed into the substrate surface which are substantially parallel to one another and extend in a second direction substantially perpendicular to the first direction, wherein each of the second regions is formed underneath one of the trenches, and wherein each of the channel region first portions extends substantially along a sidewall of one of the trenches and each of the channel region second portions extends substantially along the surface of the substrate.
17. The array of claim 16 , each of the control gates includes a first portion disposed adjacent to and insulated from a distal end of one of the floating gate first portions, and a second portion extending into one of the trenches and disposed adjacent to and insulated from one of the channel region first portions.
18. The array of claim 16 , wherein each of the channel regions further includes a third portion that extends underneath at least a portion of one of the trenches.
19. The array of claim 16 , wherein for each of the channel regions, the first and second portions thereof are non-linear with respect to each other, with the channel region first portion extending in a direction directly toward one of the floating gate first portions to define a path for programming the one floating gate.
20. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material having a first conductivity type and a surface;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
each of the active regions including a plurality of memory cells, each of the memory cells comprising:
first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having first and second portions,
an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region, and
an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion; and
a plurality of trenches formed into the substrate surface which are substantially parallel to one another and extend in a second direction substantially perpendicular to the first direction, wherein each of the first regions is formed underneath one of the trenches, and wherein each of the channel region second portions extends substantially along a sidewall of one of the trenches and each of the channel region first portions extends substantially along the surface of the substrate.
21. The array of claim 20 , wherein each of the floating gate second portions extends over and is insulated from a bottom surface of one of the trenches, and wherein each of the floating gate first portions extends along and is insulated from one of the trench sidewalls.
22. The array of claim 21 , wherein each of the floating gate first portions includes an upper segment that extends above the substrate surface, and wherein each of the control gates is disposed laterally adjacent to and insulated from one of the floating gate upper segments.
23. The array of claim 22 , wherein each of the control gates includes a portion disposed over and insulated from a distal end of one of the floating gate upper segments.
24. The array of claim 20 , further comprising:
a plurality of conductive material blocks each having at least a lower portion thereof disposed in one of the trenches laterally adjacent to and insulated from one of the floating gates.
25. The array of claim 24 , wherein the lower portion of each of the conductive material blocks is disposed over and insulated from one of the first regions.