Charge pump circuit and a novel capacitor for a memory integrated circuit
View Patent ↗A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode. A fourth electrode is adjacent to and spaced apart from the third electrode in the second plane and is capacitively coupled to the third electrode and capacitively coupled to the second electrode. The first and fourth electrodes are electrically connected together and the second and third electrodes are electrically connected together. In addition, a cylindrical shape electrode, and a great wall electrode, and charge pump capacitor-by-pattern-filling is disclosed. A charge pump circuit using the foregoing described capacitor has a plurality of transistors for charging the capacitor and discharging the capacitor thereby increasing the voltage of the charge pump circuit.
1. A charge pump circuit for use in an integrated circuit die, said charge pump circuit comprising:
a capacitor;
a plurality of transistors for charging said capacitor and discharging said capacitor thereby increasing the voltage of the charge pump circuit; and
said capacitor comprises:
a first electrode in a first plane, wherein said first electrode comprises a plurality of first interdigital elements electrically connected to one another;
a second electrode adjacent to and spaced apart from the first electrode in the first plane and capacitively coupled thereto, wherein said second electrode comprises a plurality of second interdigital elements electrically connected to one another, with each second interdigital element between a pair of first interdigital elements;
a third electrode in a second plane, spaced apart from the first plane and capacitively coupled to the first electrode, wherein said third electrode comprises a plurality of third interdigital elements electrically connected to one another, with each third interdigital element capacitively coupled to a different first interdigital element; and
a fourth electrode adjacent to and spaced apart from the third electrode in the second plane and capacitively coupled to the third electrode and capacitively coupled to the second electrode, wherein said fourth electrode comprises a plurality of fourth interdigital elements electrically connected to one another, with each fourth interdigital element between a pair of third interdigital elements, and with each fourth interdigital element capacitively coupled to a different second interdigital element;
wherein said first and fourth electrodes are electrically connected and said second and third electrodes are electrically connected;
wherein said integrated circuit die further comprises:
a semiconductor substrate having a first conductivity, said substrate having a planar surface;
a first region of a second conductivity on said planar surface of said substrate;
wherein said first region is electrically connected to said first electrode.
2. The charge pump circuit of claim 1 further comprising:
a planar electrode above the planar surface of said substrate, and insulated therefrom;
wherein the planar electrode is electrically connected to said second electrode.
3. The charge pump circuit of claim 2 further comprising
a bonding pad above the planar surface of said substrate;
wherein said capacitor is positioned between the bonding pad and the planar surface of said substrate.
4. The charge pump circuit of claim 2 wherein said planar electrode is made of polysilicon and wherein each of said first electrode, second electrode, third electrode and fourth electrode is made of metal.
5. The charge pump circuit of claim 1 , wherein each of said plurality of first interdigital elements are parallel to one another in a first direction; wherein each of said plurality of second interdigital elements are parallel to one another in said first direction; wherein each of said plurality of third interdigital elements are parallel to one another in said first direction; and wherein each of said plurality of fourth interdigital elements are parallel to one another in said first direction.
6. The charge pump circuit of claim 5
wherein each of said first interdigital elements further comprises a plurality of first fingers extending in a second direction not parallel to the first direction from a first interdigital element;
wherein each of said second interdigital elements further comprises a plurality of second fingers extending in said second direction from a second interdigital element;
wherein each of said third interdigital elements further comprises a plurality of third fingers extending in said second direction from a third interdigital element;
wherein each of said fourth interdigital elements further comprises a plurality of fourth fingers extending in said second direction from a fourth interdigital element.
7. The charge pump circuit of claim 6
wherein each of said first fingers are spaced apart from one;
wherein each of said second fingers are spaced apart from one another with a second finger between a pair of first fingers;
wherein each of said third fingers are spaced apart from one;
wherein each of said fourth fingers are spaced apart from one another with a fourth finger between a pair of third fingers; and
wherein said second direction is substantially perpendicular to said first direction.
8. A capacitor comprising:
a semiconductor substrate having a planar surface;
a first electrode in a first plane spaced apart from the planar surface wherein said first electrode comprises a plurality of first interdigital elements electrically connected to one another;
a second electrode adjacent to and spaced apart from the first electrode in the first plane and capacitively coupled thereto, wherein said second electrode comprises a plurality of second interdigital elements electrically connected to one another, with each second interdigital element between a pair of first interdigital elements;
a third electrode in a second plane, spaced apart from the first plane and capacitively coupled to the first electrode, wherein said third electrode comprises a plurality of third interdigital elements electrically connected to one another, with each third interdigital element capacitively coupled to a different first interdigital element; and
a fourth electrode adjacent to and spaced apart from the third electrode in the second plane and capacitively coupled to the third electrode and capacitively coupled to the second electrode, wherein said fourth electrode comprises a plurality of fourth interdigital elements electrically connected to one another, with each fourth interdigital element between a pair of third interdigital elements, and with each fourth interdigital element capacitively coupled to a different second interdigital element;
wherein said first and fourth electrodes are electrically connected and said second and third electrodes are electrically connected;
wherein said substrate has a first conductivity;
a first region of a second conductivity on said planar surface of said substrate;
wherein said first region is electrically connected to said first electrode.
9. The capacitor of claim 8 further comprising:
a planar electrode above the planar surface of said substrate, and insulated therefrom;
wherein the planar electrode is electrically connected to said second electrode.
10. The capacitor of claim 9 further comprising
a bonding pad above the planar surface of said substrate;
wherein said capacitor is positioned between the bonding pad and the planar surface of said substrate.
11. The capacitor of claim 9 wherein said planar electrode is made of polysilicon and wherein each of said first electrode, second electrode, third electrode and fourth electrode is made of metal.
12. The capacitor of claim 8 , wherein each of said plurality of first interdigital elements are parallel to one another in a first direction; wherein each of said plurality of second interdigital elements are parallel to one another in said first direction; wherein each of said plurality of third interdigital elements are parallel to one another in said first direction; and wherein each of said plurality of fourth interdigital elements are parallel to one another in said first direction.
13. The capacitor of claim 12
wherein each of said first interdigital elements further comprises a plurality of first fingers extending in a second direction not parallel to the first direction from a first interdigital element;
wherein each of said second interdigital elements further comprises a plurality of second fingers extending in said second direction from a second interdigital element;
wherein each of said third interdigital elements further comprises a plurality of third fingers extending in said second direction from a third interdigital element;
wherein each of said fourth interdigital elements further comprises a plurality of fourth fingers extending in said second direction from a fourth interdigital element.
14. The capacitor of claim 13
wherein each of said first fingers are spaced apart from one;
wherein each of said second fingers are spaced apart from one another with a second finger between a pair of first fingers;
wherein each of said third fingers are spaced apart from one;
wherein each of said fourth fingers are spaced apart from one another with a fourth finger between a pair of third fingers; and
wherein said second direction is substantially perpendicular to said first direction.