Method of programming a non-volatile memory cell
View Patent ↗The present invention relates to a method of a programming a select non-volatile memory cell in a plurality of serially connected non-volatile memory cells with a serially connected select transistor. Each of the non-volatile memory cells has a control gate for receiving a programming voltage and the select transistor has a select gate for receiving a select voltage. The method comprises applying the programming voltage to the control gate of the select non-volatile memory cell in a program command sequence. The magnitude of the select voltage to the select gate of the select transistor within the program command sequence is then varied. The method can be applied to non-volatile cells in a NAND or NOR architecture.
1. A method of programming a select non-volatile memory cell having an associated select transistor, wherein said non-volatile memory cell having a control gate for receiving a programming voltage and wherein said select transistor having a select gate for receiving a select voltage, said method comprising:
applying said programming voltage to said control gate of said select non-volatile memory cell in a program command sequence, said program command sequence comprising a plurality of separate pulses of programming voltage applied to said control gate of said select non-volatile memory cell, and a plurality of separate pulses of select voltage applied to said select gate of said select transistor, each pulse of select voltage corresponding to a pulse of programming voltage; and
varying the magnitude of each of said separate pulses of said select voltage to said select gate of said select transistor during said program command sequence.
2. A method of programming a select non-volatile memory cell having an associated select transistor, wherein said select non-volatile memory cell having a control gate for receiving a programming voltage and wherein said select transistor having a select gate for receiving a select voltage, said method comprising:
applying a single pulse of programming voltage applied to said control gate of said select non-volatile memory cell; and
continuously ramping up said select voltage until a maximum is reached.
3. A method of programming a select non-volatile memory cell having an associated select transistor, wherein said select non-volatile memory cell having a control gate for receiving a programming voltage and wherein said select transistor having a select gate for receiving a select voltage, said method comprising:
applying a single pulse of programming voltage applied to said control gate of said select non-volatile memory cell; and
increasing said select voltage in a plurality of steps that increase in magnitude.
4. A method of programming a select non-volatile memory cell having an associated select transistor, wherein said select non-volatile memory cell having a control gate for receiving a programming voltage and wherein said select transistor having a select gate for receiving a select voltage, said method comprising:
applying a single pulse of programming voltage applied to said control gate of said select non-volatile memory cell; and
continuously ramping down said select voltage until a minimum is reached.
5. A method of programming a select non-volatile memory cell having an associated select transistor, wherein said select non-volatile memory cell having a control gate for receiving a programming voltage and wherein said select transistor having a select gate for receiving a select voltage, said method comprising:
applying a single pulse of programming voltage applied to said control gate of said select non-volatile memory cell; and
decreasing said select voltage in a plurality of steps that decrease in magnitue.
6. The method of claim 1 , 2 , 3 , 4 and 5 wherein said select non-volatile memory cell is in a plurality of serially connected non-volatile memory cells with the plurality of serially connected non-volatile memory cells having the associated select transistor serially connected thereto.
7. The method of claim 6 wherein said associated select transistor is serially electrically connected between a pair of non-volatile memory cells, and wherein said associated select transistor is immediately adjacent to and is directly and serially connected to said select non-volatile memory cell.
8. The method of claim 1 , 2 , 3 , 4 and 5 wherein said select non-volatile memory cell is directly and serially connected to the associated select transistor.