Array Of Non-volatile Memory Cells With ROM Cells
A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.
1 . A memory device, comprising:
a semiconductor substrate;
a plurality of ROM cells, wherein each of the ROM cells comprises:
spaced apart source and drain regions formed in the substrate, with a channel region therebetween,
a first gate disposed over and insulated from a first portion of the channel region,
a second gate disposed over and insulated from a second portion of the channel region,
a conductive line extending over the plurality of ROM cells,
wherein the conductive line is electrically coupled to the drain regions of a first subgroup of the plurality of ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the plurality of ROM cells; and
a plurality of NVM cells, wherein each of the NVM cells comprises:
spaced apart second source and second drain regions formed in the substrate, with a second channel region therebetween,
a floating gate disposed over and insulated from a first portion of the second channel region,
a select gate disposed over and insulated from a second portion of the channel region.
2 . The memory device of claim 1 , wherein each of the NVM cells further comprises:
a control gate disposed over and insulated from the floating gate; and
an erase gate disposed over and insulated from the second source region.
3 . The memory device of claim 1 , wherein each of the drain regions of the first subgroup of the plurality of ROM cells are electrically coupled to the conductive line by a conductive contact extending from the drain region to the conductive line.
4 . The memory device of claim 3 , wherein each of the second subgroup of the plurality of ROM cells lack any conductive contact extending from the drain region.
5 . The memory device of claim 1 , further comprising:
a plurality of dummy gates disposed over and insulated from the substrate, wherein each of the dummy gates is disposed between two of the drain regions.
6 . The memory device of claim 1 , wherein each of the ROM cells further comprises:
a third gate disposed over and insulated from the first gate.
7 . The memory device of claim 1 , wherein each of the ROM cells further comprises:
a third gate disposed over and electrically coupled to the first gate.
8 . The memory device of claim 3 , wherein each of the second subgroup of the plurality of ROM cells further comprises:
a layer of insulation material disposed on the drain region; and
a conductive contact extending between the layer of insulation material and the conductive line.